Datasheet

ADS41B29
ADS41B49
www.ti.com SBAS486E – NOVEMBER 2009–REVISED JULY 2012
Register Address 40h (Default = 00h)
7 6 5 4 3 2 1 0
CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM
PATTERN D7 PATTERN D6 PATTERN D5 PATTERN D4 PATTERN D3 PATTERN D2 PATTERN D1 PATTERN D0
Bits[7:0] CUSTOM PATTERN
(1)
These bits set the custom pattern.
(1) For the ADS41B4x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS41B2x, output data bits 11 to 0 are CUSTOM
PATTERN D[13:2].
Register Address 41h (Default = 00h)
7 6 5 4 3 2 1 0
EN CLKOUT EN CLKOUT
LVDS CMOS CMOS CLKOUT STRENGTH CLKOUT RISE POSN
RISE FALL
Bits[7:6] LVDS CMOS: Interface selection
These bits select the interface.
00, 10 = The DFS pin controls the selection of either LVDS or CMOS interface
01 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4] CMOS CLKOUT STRENGTH
Controls strength of CMOS output clock only.
00 = Maximum strength (recommended and used for specified timings)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bit 3 ENABLE CLKOUT RISE
0 = Disables control of output clock rising edge
1 = Enables control of output clock rising edge
Bits[2:1] CLKOUT RISE POSN: CLKOUT rise control
Controls position of output clock rising edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 500ps, hold increases by 500ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200ps, hold increases by 200ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 100ps, hold increases by 100ps
10 = Setup reduces by 200ps, hold increases by 200ps
11 = Setup reduces by 1.5ns, hold increases by 1.5ns
Bit 0 ENABLE CLKOUT FALL
0 = Disables control of output clock fall edge
1 = Enables control of output clock fall edge
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