Datasheet

ADS41B29
ADS41B49
SBAS486E – NOVEMBER 2009–REVISED JULY 2012 www.ti.com
Register Address 26h (Default = 00h)
7 6 5 4 3 2 1 0
LVDS CLKOUT LVDS DATA
0 0 0 0 0 0
STRENGTH STRENGTH
Bits[7:2] Always write '0'
Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength
This bit determines the external termination to be used with the LVDS output clock buffer.
0 = 100Ω external termination (default strength)
1 = 50Ω external termination (2x strength)
Bit 0 LVDS DATA STRENGTH: LVDS data buffer strength
This bit determines the external termination to be used with all of the LVDS data buffers.
0 = 100Ω external termination (default strength)
1 = 50Ω external termination (2x strength)
Register Address 3Dh (Default = 00h)
7 6 5 4 3 2 1 0
EN OFFSET
DATA FORMAT 0 0 0 0 0
CORR
Bits[7:6] DATA FORMAT: Data format selection
These bits selects the data format.
00 = The DFS pin controls data format selection
10 = Twos complement
11 = Offset binary
Bit 5 ENABLE OFFSET CORR: Offset correction setting
This bit sets the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0] Always write '0'
Register Address 3Fh (Default = 00h)
7 6 5 4 3 2 1 0
CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM CUSTOM
0 0
PATTERN D13 PATTERN D12 PATTERN D11 PATTERN D10 PATTERN D9 PATTERN D8
Bits[7:6] Always write '0'
Bits[5:0] CUSTOM PATTERN
(1)
These bits set the custom pattern.
(1) For the ADS41B4x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS41B2x, output data bits 11 to 0 are CUSTOM
PATTERN D[13:2].
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