Datasheet

ADS41B29

ADS41B49

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SBAS486E – NOVEMBER 2009–REVISED JULY 2012

7 6 5 4 3 2 1 0

GAIN 0 TEST PATTERNS

Bits[7:4] GAIN: Gain programmability

These bits set the gain programmability in 0.5dB steps.

0000, 0001, 0010, 0011, 0100 = Do not use

0101 = 0dB gain (default after reset)

0110 = 0.5dB gain

0111 = 1dB gain

1000 = 1.5dB gain

1001 = 2dB gain

1010 = 2.5dB gain

1011 = 3dB gain

1100 = 3.5dB gain

Bit 3 Always write '0'

Bits[2:0] TEST PATTERNS: Data capture

These bits verify data capture.

000 = Normal operation

001 = Outputs all 0s

010 = Outputs all 1s

011 = Outputs toggle pattern

In the ADS41B49, output data D[13:0] is an alternating sequence of 01010101010101 and

10101010101010.

In the ADS41B29, output data D[11:0] is an alternating sequence of 010101010101 and

101010101010.

100 = Outputs digital ramp

In ADS41B46, output data increments by one LSB (14-bit) every clock cycle from code 0 to

code 16383

In ADS41B26, output data increments by one LSB (12-bit) every 4th clock cycle from code 0 to

code 4095

101 = Output custom pattern (use registers 0x3F and 0x40 for setting the custom pattern)

110 = Unused

111 = Unused

Product Folder Link(s): ADS41B29 ADS41B49