Datasheet

AVDD
(5/8)AVDD
(3/8)AVDD
3R
2R
3R
(3/8)AVDD
(5/8)AVDD
AVDDGND
ToParallelPin
ADS41B29
ADS41B49
www.ti.com SBAS486E – NOVEMBER 2009–REVISED JULY 2012
DEVICE CONFIGURATION
The ADS41B29/49 have several modes that can be configured using a serial programming interface, as
described in Table 4, Table 5, and Table 6. In addition, the devices have two dedicated parallel pins for quickly
configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital
control pin). The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance
resistors).
Table 4. DFS: Analog Control Pin
DESCRIPTION
VOLTAGE APPLIED ON DFS (Data Format/Output Interface)
0, +100mV/0mV Twos complement/DDR LVDS
(3/8) AVDD ± 100mV Twos complement/parallel CMOS
(5/8) AVDD ± 100mV Offset binary/parallel CMOS
AVDD, 0mV/–100mV Offset binary/DDR LVDS
Table 5. OE: Digital Control Pin
VOLTAGE APPLIED ON OE DESCRIPTION
0 Output data buffers disabled
AVDD Output data buffers enabled
When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device
in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have
any alternative functions. Keep SEN tied high and SCLK tied low on the board.
Table 6. SDATA: Digital Control Pin
VOLTAGE APPLIED ON SDATA DESCRIPTION
0 Normal operation
Logic high Device enters standby
Figure 8. Simplified Diagram to Configure DFS Pin
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Product Folder Link(s): ADS41B29 ADS41B49