Datasheet

O
E
O
E
O
E
O
E
O
EE
O
E
O
E
O
E
O
E
O
N+1 N+2
InputClock
CLKOUTM
CLKOUTP
OutputData
(2)
(DXP,DXM)
DDRLVDS
N 1- N N+1
CLKOUT
OutputData
ParallelCMOS
InputSignal
SampleN
N+1
N+2
N+3 N+4
N+21
N+22
N+23
t
A
t
SU
t
SU
t
H
t
H
t
PDI
t
PDI
CLKP
CLKM
N 21- N 21- N 19- N 18-
N 21- N 20- N 19-
N 18-
N 17-
21ClockCycles
(1)
N
21ClockCycles
(1)
ADS41B29
ADS41B49
www.ti.com SBAS486E – NOVEMBER 2009–REVISED JULY 2012
(1) At higher sampling frequencies, t
DPI
is greater than one clock cycle which then makes the overall latency = ADC latency + 1.
(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).
Figure 5. Latency Diagram
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