Datasheet

ADS41B29
ADS41B49
SBAS486E – NOVEMBER 2009–REVISED JULY 2012 www.ti.com
Table 1. LVDS Timing Across Sampling Frequencies
SAMPLING SETUP TIME (ns) HOLD TIME (ns)
FREQUENCY
(MSPS) MIN TYP MAX MIN TYP MAX
230 0.85 1.25 0.35 0.6
200 1.05 1.55 0.35 0.6
185 1.1 1.7 0.35 0.6
160 1.6 2.1 0.35 0.6
125 2.3 3 0.35 0.6
80 4.5 5.2 0.35 0.6
Table 2. CMOS Timing Across Sampling Frequencies
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
SAMPLING
t
SETUP
(ns) t
HOLD
(ns) t
PDI
(ns)
FREQUENCY
(MSPS) MIN TYP MAX MIN TYP MAX MIN TYP MAX
200 1 1.6 2 2.8 4 5.5 7
185 1.3 2 2.2 3 4 5.5 7
160 1.8 2.5 2.5 3.3 4 5.5 7
125 2.5 3.2 3.5 4.3 4 5.5 7
80 4.8 5.5 5.7 6.5 4 5.5 7
Table 3. CMOS Timing Across Sampling Frequencies
TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK
t
START
(ns) t
DV
(ns)
SAMPLING FREQUENCY
(MSPS) MIN TYP MAX MIN TYP MAX
250 1.6 2.5 3.2
230 1.1 2.9 3.5
200 0.3 3.5 4.2
185 0 3.9 4.5
170 –1.3 4.3 5
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