Datasheet

ADS41B29
ADS41B49
www.ti.com SBAS486E – NOVEMBER 2009–REVISED JULY 2012
TIMING REQUIREMENTS: LVDS and CMOS Modes
(1)
Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave
input clock, C
LOAD
= 5pF
(2)
, and R
LOAD
= 100Ω
(3)
, unless otherwise noted. Minimum and maximum values are across the full
temperature range: T
MIN
= –40°C to T
MAX
= +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.7V to 1.9V.
PARAMETER CONDITIONS MIN TYP MAX UNIT
t
A
Aperture delay 0.6 0.8 1.2 ns
Variation of Between two devices at
±100 ps
aperture delay the same temperature and DRVDD supply
t
J
Aperture jitter 100 f
S
rms
Time to valid data after coming out of STANDBY mode 5 25 µs
Wakeup time
Time to valid data after coming out of PDN GLOBAL mode 100 500 µs
Clock
Gain enabled (default after reset) 21
cycles
ADC latency
(4)
Clock
Gain and offset correction enabled 22
cycles
DDR LVDS MODE
t
SU
Data setup time
(5)
Data valid
(6)
to zero-crossing of CLKOUTP 0.75 1.1 ns
t
H
Data hold time
(5)
Zero-crossing of CLKOUTP to data becoming invalid
(6)
0.35 0.6 ns
Input clock rising edge cross-over to
t
PDI
Clock propagation delay output clock rising edge cross-over 3 4.2 5.4 ns
1MSPS ≤ sampling frequency ≤ 250MSPS
Between two devices at
Variation of t
PDI
±0.6 ns
the same temperature and DRVDD supply
LVDS bit Duty cycle of differential clock, (CLKOUTP – CLKOUTM)
42 48 54 %
clock duty cycle 1MSPS ≤ sampling frequency ≤ 250MSPS
Rise time measured from –100mV to +100mV
Data rise time,
t
RISE
, t
FALL
Fall time measured from +100mV to –100mV 0.14 ns
Data fall time
1MSPS ≤ sampling frequency ≤ 250MSPS
Rise time measured from –100mV to +100mV
t
CLKRISE
, Output clock rise time,
Fall time measured from +100mV to –100mV 0.14 ns
t
CLKFALL
Output clock fall time
1MSPS ≤ sampling frequency ≤ 250MSPS
Output enable (OE) to
t
OE
Time to valid data after OE becomes active 50 100 ns
data delay
PARALLEL CMOS MODE
(7)
t
START
Input clock to data delay Input clock rising edge cross-over to start of data valid
(6)
1.6 ns
t
DV
Data valid time Time interval of valid data
(6)
2.5 3.2 ns
Input clock rising edge cross-over to
t
PDI
Clock propagation delay output clock rising edge cross-over 4 5.5 7 ns
1MSPS ≤ sampling frequency ≤ 200MSPS
Duty cycle of output clock, CLKOUT
Output clock duty cycle 47 %
1MSPS ≤ sampling frequency ≤ 200MSPS
Rise time measured from 20% to 80% of DRVDD
Data rise time,
t
RISE
, t
FALL
Fall time measured from 80% to 20% of DRVDD 0.35 ns
Data fall time
1 ≤ sampling frequency ≤ 250MSPS
Rise time measured from 20% to 80% of DRVDD
t
CLKRISE
, Output clock rise time,
Fall time measured from 80% to 20% of DRVDD 0.35 ns
t
CLKFALL
Output clock fall time
1 ≤ sampling frequency ≤ 200MSPS
Output enable (OE) to
t
OE
Time to valid data after OE becomes active 20 40 ns
data delay
(1) Timing parameters are ensured by design and characterization but are not production tested.
(2) C
LOAD
is the effective external single-ended load capacitance between each output pin and ground.
(3) R
LOAD
is the differential load resistance between the LVDS output pair.
(4) At higher frequencies, t
PDI
is greater than one clock period and overall latency = ADC latency + 1.
(5) R
LOAD
is the differential load resistance between the LVDS output pair.
(6) Data valid refers to a logic high of 1.26V and a logic low of 0.54V.
(7) For f
S
> 200MSPS, it is recommended to use an external clock for data capture instead of the device output clock signal (CLKOUT).
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