Datasheet

Dn_Dn+1_P
Dn_Dn+1_M
GND
Logic0
V
ODL
Logic1
V
ODH
V
OCM
14-Bit
ADC
OVR_SDOUT
D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
CLKOUTM
CLKOUTP
CLKM
CLKP
CLOCKGEN
INM
VCM
INP
Sampling
Circuit
Common
DigitalFunctions
DDR
Serializer
Reference
OE
Control
Interface
SDATA
DFS
SEN
SCLK
RESET
ADS41B49
AVDD
AGND DRVDD DRGND
DDRLVDS
Interface
D12_D13_M
D12_D13_P
AnalogBuffers
AVDD_BUF
ADS41B29
ADS41B49
SBAS486E – NOVEMBER 2009–REVISED JULY 2012 www.ti.com
FUNCTIONAL BLOCK DIAGRAM
Figure 3. ADS41B49 Block Diagram
TIMING CHARACTERISTICS
(1) With external 100Ω termination.
Figure 4. LVDS Output Voltage Levels
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Product Folder Link(s): ADS41B29 ADS41B49