Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Internal VQFN 48

ADS41B29

ADS41B49

www.ti.com

SBAS486E – NOVEMBER 2009–REVISED JULY 2012

14-/12-Bit, 250MSPS, Ultralow-Power ADC

with Analog Buffers

Check for Samples: ADS41B29, ADS41B49

FEATURES

DESCRIPTION

The ADS41B29/B49 are members of the ultralow-

• ADS41B49: 14-Bit, 250MSPS

power ADS4xxx analog-to-digital converter (ADC)

ADS41B29: 12-Bit, 250MSPS

family, featuring integrated analog input buffers.

• Integrated High-Impedance

These devices use innovative design techniques to

Analog Input Buffer:

achieve high dynamic performance, while consuming

extremely low power. The analog input pins have

– Input Capacitance: 2pF

buffers, with benefits of constant performance and

– 200MHz Input Resistance: 3kΩ

input impedance across a wide frequency range. The

• Maximum Sample Rate: 250MSPS

devices are well-suited for multi-carrier, wide

• Ultralow Power:

bandwidth communications applications such as PA

linearization.

– 1.8V Analog Power: 180mW

The ADS41B49/29 have features such as digital gain

– 3.3V Buffer Power: 96mW

and offset correction. The gain option can be used to

– I/O Power: 135mW (DDR LVDS)

improve SFDR performance at lower full-scale input

• High Dynamic Performance:

ranges, especially at high input frequencies. The

– SNR: 69dBFS at 170MHz

integrated dc offset correction loop can be used to

estimate and cancel the ADC offset. At lower

– SFDR: 82.5dBc at 170MHz

sampling rates, the ADC automatically operates at

• Output Interface:

scaled-down power with no loss in performance.

– Double Data Rate (DDR) LVDS with

The devices support both double data rate (DDR)

Programmable Swing and Strength:

low-voltage differential signaling (LVDS) and parallel

– Standard Swing: 350mV

CMOS digital output interfaces. The low data rate of

the DDR LVDS interface (maximum 500MBPS)

– Low Swing: 200mV

makes it possible to use low-cost field-programmable

– Default Strength: 100Ω Termination

gate array (FPGA)-based receivers. The devices

– 2x Strength: 50Ω Termination

have a low-swing LVDS mode that can be used to

– 1.8V Parallel CMOS Interface Also further reduce the power consumption. The strength

of the LVDS output buffers can also be increased to

Supported

support 50Ω differential termination.

• Programmable Gain for SNR/SFDR Trade-Off

The devices are available in a compact QFN-48

• DC Offset Correction

package and are specified over the industrial

• Supports Low Input Clock Amplitude

temperature range (–40°C to +85°C).

• Package: QFN-48 (7mm × 7mm)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments, Incorporated.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (65 pages)

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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 14-/12-Bit, 250MSPS, Ultralow-Power ADC with Analog Buffers Check for Samples: ADS41B29, ADS41B49 FEATURES DESCRIPTION • The ADS41B29/B49 are members of the ultralowpower ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 RECOMMENDED OPERATING CONDITIONS ADS41B29, ADS41B49 MIN TYP MAX UNIT 1.7 1.8 1.9 V 3 3.3 3.6 V 1.7 1.8 1.9 V SUPPLIES AVDD Analog supply voltage AVDD_BUF Analog buffer supply voltage DRVDD Digital supply voltage ANALOG INPUTS Differential input voltage range (1) 1.5 Input common-mode voltage VPP 1.7 ± 0.05 V Maximum analog input frequency with 1.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: ADS41B29, ADS41B49 Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, 1.5VPP clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 ELECTRICAL CHARACTERISTICS: GENERAL Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, and 50% clock duty cycle, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V. ADS41B29, ADS41B49 PARAMETER MIN TYP MAX UNIT ANALOG INPUTS Differential input voltage range 1.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com DIGITAL CHARACTERISTICS Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V. ADS41B29, ADS41B49 PARAMETER TEST CONDITIONS MIN RESET, SCLK, SDATA, and SEN support 1.8V and 3.3V CMOS logic levels 1.3 OE only supports 1.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 ADS41B49, ADS41B29 Pin Descriptions (LVDS Mode) (continued) PIN NAME PIN NUMBER # OF PINS FUNCTION DESCRIPTION SEN 27 1 I This pin functions as a serial interface enable input when RESET is low. When RESET is high, SEN has no function and should be tied to AVDD. This pin has an internal 180kΩ pull-up resistor to AVDD.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 TIMING REQUIREMENTS: LVDS and CMOS Modes (1) Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock, CLOAD = 5pF (2), and RLOAD = 100Ω (3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.7V to 1.9V.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com Table 1. LVDS Timing Across Sampling Frequencies SAMPLING FREQUENCY (MSPS) SETUP TIME (ns) MIN TYP 230 0.85 200 1.05 185 HOLD TIME (ns) MAX MIN TYP 1.25 0.35 0.6 1.55 0.35 0.6 1.1 1.7 0.35 0.6 160 1.6 2.1 0.35 0.6 125 2.3 3 0.35 0.6 80 4.5 5.2 0.35 0.6 MAX Table 2.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com CLKM Input Clock CLKP tPDI CLKOUTP Output Clock CLKOUTM tSU Output Dn_Dn + 1_P Data Pair Dn_Dn + 1_M tSU tH Dn (1) tH Dn + 1 (1) (1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc. Figure 6. LVDS Mode Timing CLKM Input Clock CLKP tPDI Output Clock CLKOUT tSU Output Data Dn tH Dn (1) CLKM Input Clock CLKP tSTART tDV Output Data Dn Dn (1) Dn = bits D0, D1, D2, etc. Figure 7.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 DEVICE CONFIGURATION The ADS41B29/49 have several modes that can be configured using a serial programming interface, as described in Table 4, Table 5, and Table 6. In addition, the devices have two dedicated parallel pins for quickly configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin).
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com SERIAL INTERFACE The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every falling edge of SCLK when SEN is active (low).
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 Serial Register Readout The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC. After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com RESET TIMING CHARACTERISTICS Power Supply AVDD, DRVDD t1 RESET t3 t2 SEN NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET must be permanently tied high. Figure 11.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 SERIAL REGISTER MAP Table 7 summarizes the functions supported by the serial interface. Table 7.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 Register Address 25h (Default = 50h) 7 6 5 4 GAIN Bits[7:4] 3 0 2 1 0 TEST PATTERNS GAIN: Gain programmability These bits set the gain programmability in 0.5dB steps. 0000, 0001, 0010, 0011, 0100 = Do not use 0101 = 0dB gain (default after reset) 0110 = 0.5dB gain 0111 = 1dB gain 1000 = 1.5dB gain 1001 = 2dB gain 1010 = 2.5dB gain 1011 = 3dB gain 1100 = 3.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com Register Address 26h (Default = 00h) 7 6 0 5 0 4 0 3 0 0 2 1 0 0 LVDS CLKOUT STRENGTH LVDS DATA STRENGTH Bits[7:2] Always write '0' Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength This bit determines the external termination to be used with the LVDS output clock buffer.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 Register Address 40h (Default = 00h) 7 6 5 4 3 2 1 0 CUSTOM PATTERN D7 CUSTOM PATTERN D6 CUSTOM PATTERN D5 CUSTOM PATTERN D4 CUSTOM PATTERN D3 CUSTOM PATTERN D2 CUSTOM PATTERN D1 CUSTOM PATTERN D0 Bits[7:0] CUSTOM PATTERN (1) These bits set the custom pattern. (1) For the ADS41B4x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS41B2x, output data bits 11 to 0 are CUSTOM PATTERN D[13:2].
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 Register Address 43h (Default = 00h) 7 6 5 4 3 2 1 0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING Bit 0 Always write '0' Bit 6 PDN GLOBAL: Power-down 0 This bit sets the state of operation. 0 = Normal operation 1 = Total power down; the ADC, internal references, and output buffers are powered down; slow wake-up time.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com Register Address BFh (Default = 00h) 7 6 5 4 3 2 OFFSET PEDESTAL Bits[7:2] 1 0 0 0 OFFSET PEDESTAL These bits set the offset pedestal. When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 Register Address CFh (Default = 00h) 7 6 FREEZE OFFSET CORR 0 Bit 7 5 4 3 2 OFFSET CORR TIME CONSTANT 1 0 0 0 FREEZE OFFSET CORR This bit sets the freeze offset correction. 0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set) 1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set).
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: ADS41B49 At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 90.3dBc SNR = 69.9dBFS SINAD = 69.8dBFS THD = 85.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: ADS41B49 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: ADS41B49 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: ADS41B49 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS TEMPERATURE vs AVDD SUPPLY SNR ACROSS TEMPERATURE vs AVDD SUPPLY 69.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: ADS41B49 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE INTEGRAL NONLINEARITY 71 92 Input Frequency = 10MHz 2.5 THD SNR 2 1.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: ADS41B29 At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. FFT FOR 20MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL 0 0 SFDR = 89.6dBc SNR = 68.6dBFS SINAD = 68.5dBFS THD = 85.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: ADS41B29 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: ADS41B29 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: ADS41B29 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SFDR ACROSS TEMPERATURE vs AVDD SUPPLY SNR ACROSS TEMPERATURE vs AVDD SUPPLY 68.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: ADS41B29 (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE 69 95 THD SNR 90 68.5 85 68 80 67.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: GENERAL At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. CMRR ACROSS FREQUENCY CMRR FFT 0 0 fIN = 170MHz fCM = 10MHz, 50mVPP SFDR = 77.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: GENERAL (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 TYPICAL CHARACTERISTICS: CONTOUR (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SNR CONTOUR (0dB Gain, Applies to ADS41B49) 250 240 69 Sampling Frequency (MSPS) 220 68 69.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com TYPICAL CHARACTERISTICS: CONTOUR (continued) At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted. SNR CONTOUR (0dB Gain, Applies to ADS41B29) 250 240 Sampling Frequency (MSPS) 220 67 68.5 68 200 67.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 APPLICATION INFORMATION THEORY OF OPERATION The ADS41B49/29 is a family of buffered analog input and ultralow power ADCs with maximum sampling rates up to 250MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com Drive Circuit Requirements For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (5Ω to 10Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics. Figure 60 and Figure 61 show the differential impedance (ZIN = RIN || CIN) seen by looking into the ADC input pins.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 Driving Circuit Two example driving circuit configurations are shown in Figure 62 and Figure 63—one optimized for low input frequencies and the other optimized for high input frequencies. Notice in both cases that the board circuitry is simplified compared to the non-buffered ADS4149. In Figure 62, a single transformer is used and is suited for low input frequencies.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com CLOCK INPUT The ADS41B29/49 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 GAIN FOR SFDR/SNR TRADE-OFF The ADS41B29/49 include gain settings that can be used to get improved SFDR performance. The gain is programmable from 0dB to 3.5dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 8. The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by a default after reset. After a reset, the offset correction is disabled.. To use offset correction set EN OFFSET CORR to '1' and program the required time constant.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 DIGITAL OUTPUT INFORMATION The ADS41B29/49 provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the data. Output Interface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the LVDS CMOS serial interface register bit or using the DFS pin.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits, as shown in Figure 70.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 LVDS Output Data and Clock Buffers The equivalent circuit of each LVDS output buffer is shown in Figure 71. After reset, the buffer presents an output impedance of 100Ω to match with the external 100Ω termination. The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination. The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com Pins OVR CLKOUT CMOS Output Buffers D0 D1 D2 D3 ¼ ¼ 14-Bit ADC Data D11 D12 D13 ADS41B49 Figure 72.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 Use External Clock Buffer (> 200MSPS) Input Clock Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CMOS Output Buffers D0 D1 D2 CLKIN D0_In D1_In D2_In 14-Bit ADC Data D12 D13 D12_In D13_In ADS41Bx9 Use short traces between ADC output and receiver pins (1 to 2 inches). Figure 73.
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com Input Over-Voltage Indication (OVR Pin) The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists.
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 DEFINITION OF SPECIFICATIONS Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low-frequency value. Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs. This delay is different across channels. The maximum variation is specified as aperture delay variation (channel-to-channel).
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ADS41B29 ADS41B49 SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 www.ti.com Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the theoretical limit based on quantization noise. ENOB = SINAD - 1.76 6.02 (4) Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD). THD = 10Log10 PS PN (5) THD is typically given in units of dBc (dB to carrier).
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ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009 – REVISED JULY 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (December 2010) to Revision E Page • Changed Analog Inputs, Differential input capacitance parameter typical specification in Electrical Characteristics: General table .................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS41B29IRGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS41B29IRGZT VQFN RGZ 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 ADS41B49IRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS41B29IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS41B29IRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS41B49IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 ADS41B49IRGZT VQFN RGZ 48 250 336.6 336.6 28.
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