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Table 3. EVM Power Supply Options
EVM Option Evaluation Goal Jumper Changes Required Voltage on J16 Comments
1 Evaluate ADC JP13 → 1-2; JP14 → 1-2; JP17 → 1-2; 3.3 V Maximum performance and
performance using JP19 → 1-2; efficiency.
a switching power
supply (TP62562)
2 Evaluate ADC JP13 → 1-2; JP14 → 1-2; JP17 → 2-3; 3.3 V Maximum performance.
performance using JP19 → 2-3;
a LDO-based
(TPS79618)
solution.
3 Evaluate ADC JP13 → 1.8V on 2-3; JP14 → 1.8V on 2- 3.3 V Isolated power supply for
performance using 3; JP17 → open3; JP19 → open; current consumption
an isolated ADC measurements
AVDD and DVDD
for current
consumption
measurements
2.2.1.1 Power Supply Option 1
The 1.8-V rails for the ADC are generated by the TPS62562 switching regulator. The TPS62562 is a step-
down (buck) converter with an acceptable input range of up to 5.5 V. However, because other circuits on
the EVM are connected to the 3.3-V input rail, the input voltage to J16 must not exceed 3.6 V or damage
to those ICs will occur. This option complements the very low power consumption of the
ADS4xxx/58B18EVM as the TPS62562 provides excellent power efficiency.
2.2.1.2 Power Supply Option 2
Option 2 supplies power to the 1.8-V analog and digital rails of the ADC by using the TPS79618. The
TPS79618 is a low-noise dropout regulator - the 1.5-V dropout voltage (3.3 V to 1.8 V) provides sufficient
headroom for maximum PSRR and ADC performance. However, it comes at the expense of higher
system power consumption.
2.2.1.3 Power Supply Option 3
Option 3 is used to evaluate ADC performance using an isolated AVDD and DVDD power supply for
current-consumption measurements. This option must be used with caution as reversing the power supply
or connecting to the wrong connector can result in damage to the EVM. One common usage of this option
is to measure the separate current consumption of the relative supplies under particular operating
conditions. For this option, the shunts on jumpers JP13 and JP14 are removed and the input power is
supplied to the center post of the jumper. For convenience, a ground post is provided next to the center
post for header connections that contain power and ground on 0.1-inch centers.
2.2.2 Clock Input
The clock can be supplied to the ADC in several ways. The default clocking option is to supply a single-
ended clock directly to the SMA connecter, J19, directly. This clock is converted to differential and AC
coupled to the ADC by transformer coupling. The clock input must be from a clean, low-jitter source and is
commonly filtered external to the board by a narrow bandpass filter. The clock amplitude is commonly set
to about 1.5 V peak-to-peak, and the amplitude offset is not an issue due to the AC coupling of the clock
input. The clock source is commonly synchronized with the signal generator of the input frequency to keep
the clock and IF coherent for meaningful FFT analysis.
Alternatively, the clock may be supplied by an onboard VCXO and CDCE72010 clock buffer. The
CDCE72010 clock buffer has been factory programmed to output a clock to the ADC that is 1/4 the rate of
the onboard VCXO. While using this clock option, a separate 20-MHz reference clock must be supplied to
the CDCE72010 by way of the clock input SMA connector J19. From the CDCE72010, two clocking
options to the ADC are possible. A differential LVPECL clock output may be connected to the ADC clock
input or a single-ended CMOS clock from the CDCE72010 may be routed to the ADC transformer-coupled
9
SLWU067C–November 2009–Revised May 2012 ADS41xx/58B18EVM
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