Datasheet
LVDS LVDS
GND
3.3V
VSS-
VS +5V
ADC
CLKIN
IN+
J16
J11
J9
J12
IN-
J10
J19
J20
J21
J6
J8
CDC
OUT
VCXO
OUT
J5
J13
USB
R84
R24R23
R93 (bottom)
R66
R101R100
R106R99
R97
R98
R96
R82
R95
R94
R115
R113
R114
R110
R108
R107
R81
R111
R112
R86 (bottom)
R38 (bottom)R46 (bottom)
R20
R65 (bottom)
R7 (bottom)
R19 (bottom)
R67 (bottom)
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Circuit Description
Figure 2. ADS41xx/58B18 Surface Jumpers
The following sections describe the function of individual circuits. See the relevant data sheet for device
operating characteristics.
2.2.1 Power
Power is supplied to the EVM through banana jacks; from this input power, three different ways are
available of delivering power to the ADC and the other EVM functions . Figure 3 shows a simplified
representation of the power options available for the ADS41xx/58B18EVM. The default option is to provide
3.3 V to the red banana jack J16, and from there the EVM generates 1.8 V for the analog and digital
supplies to the ADC. The 1.8-V rails for the ADC can be generated from the 3.3-V input either through a
low-noise dropout regulator (TPS79618), from a switching regulator (TPS62562) for maximum power
efficiency or from an external 1.8-V power supply. The EVM also generates the proper voltages for
optional features of the EVM such as the Clock Generation circuitry, the USB circuitry, and the CMOS
output buffer.
7
SLWU067C–November 2009–Revised May 2012 ADS41xx/58B18EVM
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