Datasheet

LVDS LVDS
GND
3.3V
VSS-
VS +5V
ADC
JP13JP14
JP15
JP10
JP11
JP12
RESET
JP9
J1 J2
1
1
1
1
1
1
CLKIN
IN+
J16
J11
J9
J12
JP18
1
JP8
1
JP2
JP1
JP4
1
JP19
1
JP17
1
JP7
1
IN-
J10
J19
J20
J21
J6
J8
CDC
OUT
VCXO
OUT
SW1
SW3
SW2
J5
J13
USB
CLK EDGE 4 CLK EDGE 3 CLK EDGE 2 CLK EDGE 1
BIN, LVDS BIN, CMOS 2's, CMOS 2's, LVDS
JP3
DC/DC
LDO
OFF
THS4509
ON
ON
VCXO EN
OFF
SEN DFS
SEN
PARALLEL SERIAL
SDATA
1
JP16
ON SNRB (ADS58B18 OFF ADC OVR CDC CTRL_LE
CDC AUXSEL
CDCMODESEL
CDCPD
CDCRST
Circuit Description www.ti.com
2 Circuit Description
2.1 Schematic Diagram
The schematic diagram for this EVM can be found on the TI Web site in the relevant ADS41xx or
ADS41Bxx product folder. See the schematic or relevant section of this user's guide before changing any
jumpers.
2.2 Circuit Function
Selection of various modes of operation of the ADS41xx/58B18EVM is most often controlled by jumpers
on the EVM, either by placing shunts on 0.025-inch square jumper posts or by installation of surface
mount 0-Ω resistors. In general, the use of 0-Ω resistors as jumpers are used in the clock or signal path
where signal integrity is critical and jumper posts are used for static or low-speed control paths. Figure 1
shows the relative location of the jumpers, connectors, and switches used on the ADS41xx/58B18EVM.
Figure 2 shows the relative locations of most of the resistors and surface-mount 0-Ω jumper locations
used on the EVM. In the description of the circuit options in the following sections, each operational mode
is accompanied by a table entry that details the jumper or resistor changes that enable that option.
Figure 1 and Figure 2 can assist the user to quickly identify where these jumpers are located on the EVM.
Figure 1. ADS41xx Jumpers
6
ADS41xx/58B18EVM SLWU067C–November 2009–Revised May 2012
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