Datasheet

/125
Phase
Frequency
Detector
Charge
Pump
M divider
/128
N divider
/48
Feedback
Divider (FB)
Loop Filter
VCO
/4
Output
Divider (P)
20MHz
983.04MHz
245.76MHz
U0 (LVCMOS)
U1 (LVPECL)
3mA
160kHz
CDCE72010
¦
OUT
=
¦
VCO
P
¦ ¦
IN VCO
M
(FBxN)
£
100MHz
£
¦
OUT
1.5GHz
£
¦
IN
500MHz
£
¦
VCO
1.5GHz
=
(
(
160kHz
www.ti.com Circuit Description
2.2.2.2 Clock Option 2
Option 2 uses the onboard VCXO and CDCE72010 to provide a clock to the ADC. The CDCE72010 is
used in SPI mode which uses the internal EEPROM to configure the CDCE72010. The EEPROM is
programmed in the factory for a divide-by-4 configuration. The EEPROM configuration is shown in
Figure 4. The clock at J19 is the reference clock for CDCE72010. The VCXO frequency can be calculated
as Fvcxo = Fout x 4 (Fout is the frequency output U0 and U1). The reference clock for CDCE72010 is
calculated from Ref Clock = (Fvcxo x 125)/(48 x 128). This is the clock-to-M divider. When VCXO of
frequency 983.04 MHz is used, the calculation results in a reference clock of 20 MHz; the clock output on
Y0 pin of CDCE72010 is 245.76 MHz. This clock is filtered using the crystal filter with center frequency of
245.76 MHz. By default, the VCXO and the crystal filter are not populated on the EVM, so that the user
can populate the components depending on the end application and sampling rate. This configuration is
recommended for applications requiring an onboard clock generation scheme. The test result using this
option is shown in Figure 4.
Figure 4. CDCE72010 EEPROM Configuration Block Diagram
2.2.2.3 Clock Option 3
Option 3 is used for a differential LVPECL clock. This configuration eliminates the need for a crystal filter.
It uses the same EEPROM configuration as Option 2, but in this case, the ADC clock pins are connected
to Y1N and Y1P. The jumper setting uses the clock output Y1P and Y1N from CDCE72010, to clock ADC.
This configuration is not recommended for SNR critical applications. Notice that the clock frequency does
not change. The frequency remains the same as in Clock Option 2. The test result using this option is
shown in Figure 4.
11
SLWU067C–November 2009–Revised May 2012 ADS41xx/58B18EVM
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