Datasheet

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clock input through an onboard crystal filter. For better performance, selecting the CMOS clock through a
crystal output is recommended. Prior to making any jumper settings and resistor changes, see the
schematic located on the TI Web site in the relevant ADS41xx or ADS41Bxx product folder. Table 5
displays the various clock option settings. The VCXO and crystal filter do not come populated on the EVM
by default, although the CDCE72010 clock buffer is installed.
Table 4. Clock Input Jumper Description
EVM Jumper Description Jumper Setting
Options
JP4 ENABLE VCXO1 TC0-2111 1-2 → VCXO enabled 2-3 → VCXO disabled
J19 SMA connector for clock input
JP1 CDCE72010 power down 1-2 → CDCE72010 is power down; Open → CDCE72010 is on
JP2 CDCE72010 reset 1-2 → Reset , Open → Normal operation. (default)
R81/107 Clock In or CDC ref. jumper R81 → J19 supplies clock directly to ADC; R107 → Reference clock for
CDCE72010
R113/114/115 Clock input to +ve terminal of T4 R115 → Connects J19 to ADC; R114 → Connects Y0 output of
for ADC clock CDCE72010 (This path has crystal filter) to ADC; R113 → Connects Y1P
(Differential LVPECL clock output of CDCE72010) to ADC
R108/110 Clock input to -ve terminal of T4 for R110→ Connects to ground (Default); R108→ Connects to Y1N
ADC clock (Differential clock output of CDCE72010) only to be used with Y1P.
JP8 Mode select pin for CDCE72010 1-2 → High (default), see data sheet of CDCE72010; 2-3 → Ground
R111/112 PLLOCK LED R111 → Connects to D3 diode; R112 → Ground through 10-nF capacitor
JP10 Aux_sel pin for CDCE72010 1-2 → High, see data sheet of CDCE72010; 2-3 → Ground (Default)
Table 5. EVM Clock Input Options
Frequency
EVM Jumper and Resistor CDC Configuration
Evaluation Goal Input on Comments
Options Changes Required Description
J19
Evaluate ADC JP1 → 1-2; JP2 → no ADC's
1 performance using a shunt; JP4 → 2-3; Sampling NA Default
sinusoid clock Install: R81, R110, R115 Frequency
Evaluate ADC JP1 → no shunt; JP2 →
performance using a no shunt; JP4 → 1-2; 20M for
Divide VCXO frequency
2 crystal filtered LVCMOS Install: R107, R110, VCXO@98 Maximum performance
by 4, output on Y0
clock derived from R114; Remove: R81, 3.04 MHz
CDCE72010 R115
JP1 → no shunt; JP2 →
Divide VCXO frequency
Evaluate ADC no shunt; JP4 → 1-2; 20M for
by 4, differential Not recommended for
3 performance using a Install: R107, R108, VCXO@98
LVPECL Clock output most applications
differential LVPECL clock R114; Remove: R81, 3.04 MHz
on Y1P and Y1N
R110, R115
2.2.2.1 Clock Option 1
The Clock Option 1 provides a clock to ADC directly from an external source. For the direct supply of the
clock to the ADC, a single-ended square or sinusoidal clock input must be applied to J19. The clock
frequency must be within the maximum frequency specified for the ADC. The clock input is converted to a
differential signal by a Mini-Circuits™ ADT4-1WT, which has an impedance ratio of 4, implying that
voltage applied on J19 is stepped up by a factor of 2. ADC performance in this case depends on the clock
source quality. This option is also the default configuration on the EVM, when it is shipped from the
factory. The test result using this option is shown in Figure 10.
10
ADS41xx/58B18EVM SLWU067C–November 2009–Revised May 2012
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