ADS41xx/58B18EVM User's Guide Literature Number: SLWU067C November 2009 – Revised May 2012
Contents 1 ............................................................................................................................ 4 ................................................................................................................... 4 1.2 EVM Quick-Start Procedure ........................................................................................... 4 Circuit Description ..............................................................................................................
www.ti.com List of Figures 1 ADS41xx Jumpers .......................................................................................................... 6 2 ADS41xx/58B18 Surface Jumpers 3 4 5 6 7 8 9 10 ....................................................................................... ADS41xx/58B18EVM Power Distribution ................................................................................ CDCE72010 EEPROM Configuration Block Diagram .....................................................
User's Guide SLWU067C – November 2009 – Revised May 2012 ADS41xx/58B18EVM 1 Overview This evaluation module (EVM) user's guide gives an overview of the EVM and provides a general description of the features and functions to be considered while using this module. This EVM user's guide applies to multiple EVMs: • ADS41xx family: – ADS4126, ADS4146, ADS4128, ADS4129, ADS4149, ADS41B29, ADS41B49, ADS58B18 1.
Overview www.ti.com Table 1. Jumper List (continued) Jumper Function Default Jumper Setting ADC Circuit JP12 Parallel 1-2 JP11 SDA Open JP9 SEN 1-2 JP15 OE Open J2 DFS 7-8 J1 SEN 7-8 Clock Interface Circuit CDCE72010 (Bypassed) R81/107 CLOCK IN R81 R113/114/115 CLOCK IN, Y0, Y1P SELECT R115 R108/110 Y1N SELECT R110 JP1 PWRDWN CDC 1-2 Power Supply JP13 1.8VA_IN 1-2 JP14 1.8VD_IN 1-2 JP3 3.3V CDC 1-2 JP17 3.
Circuit Description www.ti.com 2 Circuit Description 2.1 Schematic Diagram The schematic diagram for this EVM can be found on the TI Web site in the relevant ADS41xx or ADS41Bxx product folder. See the schematic or relevant section of this user's guide before changing any jumpers. 2.2 Circuit Function Selection of various modes of operation of the ADS41xx/58B18EVM is most often controlled by jumpers on the EVM, either by placing shunts on 0.
Circuit Description www.ti.com J9 J11 J12 GND VS +5V VSS- J16 3.3V J5 R82 J8 INR84 J6 R97 R95 R46 (bottom) R99 R23 R94 IN+ R114 ADC R86 (bottom) R98 R100 LVDS R101 R24 R106 R93 (bottom) R96 R38 (bottom) R66 LVDS R20 J10 R113 R108 R19 (bottom) R115 R67 (bottom) R110 J21 VCXO OUT R107 USB J13 R111 R112 R81 R7 (bottom) R65 (bottom) J19 CLKIN J20 CDC OUT Figure 2.
Circuit Description www.ti.com TPS79618 LDO Regultor to 1.8V J16 1.8V 3.3V 1 JP17 3.3V TPS62560 Switching regulator to 1.8V 1 1 JP19 To 1.8VA JP13 J12 1 To 1.8VD GND JP14 J9 JP3 To 3.3V Clock Generator To 3.3V Buffer VSS+ THS4509 J11 VSS- Figure 3. ADS41xx/58B18EVM Power Distribution Some ADC devices that may be evaluated on the ADS41xx/58B18 platform require a 3.3-V supply for an internal front-end buffer. For this reason, an isolated 3.
Circuit Description www.ti.com Table 3. EVM Power Supply Options 2.2.1.1 EVM Option Evaluation Goal Jumper Changes Required Voltage on J16 Comments 1 Evaluate ADC performance using a switching power supply (TP62562) JP13 → 1-2; JP14 → 1-2; JP17 → 1-2; JP19 → 1-2; 3.3 V Maximum performance and efficiency. 2 Evaluate ADC performance using a LDO-based (TPS79618) solution. JP13 → 1-2; JP14 → 1-2; JP17 → 2-3; JP19 → 2-3; 3.3 V Maximum performance.
Circuit Description www.ti.com clock input through an onboard crystal filter. For better performance, selecting the CMOS clock through a crystal output is recommended. Prior to making any jumper settings and resistor changes, see the schematic located on the TI Web site in the relevant ADS41xx or ADS41Bxx product folder. Table 5 displays the various clock option settings. The VCXO and crystal filter do not come populated on the EVM by default, although the CDCE72010 clock buffer is installed. Table 4.
Circuit Description www.ti.com 2.2.2.2 Clock Option 2 Option 2 uses the onboard VCXO and CDCE72010 to provide a clock to the ADC. The CDCE72010 is used in SPI mode which uses the internal EEPROM to configure the CDCE72010. The EEPROM is programmed in the factory for a divide-by-4 configuration. The EEPROM configuration is shown in Figure 4. The clock at J19 is the reference clock for CDCE72010. The VCXO frequency can be calculated as Fvcxo = Fout x 4 (Fout is the frequency output U0 and U1).
Circuit Description 2.2.3 www.ti.com Analog Inputs The EVM can be configured to use either a transformer-coupled input or a THS4509 amplifier input, both from a single-ended source. The SMA connector J6 provides the single-ended analog input to the transformer-coupled input of the ADC. The SMA connector J8 is not installed by default, but can be used to bring a differential input clock to the transformer-coupled input or to bring a single-ended input to the THS4509 input circuit.
TI ADC SPI Control Interface www.ti.com 2.2.3.2 Analog Input Option 2 Option 2 allows the use of an amplifier to provide input to the ADC. TI has a range of wideband operational amplifiers such as THS4508/09/11/13/20. On this EVM, THS4509 is used as an example to amplify the input from J8. The THS4509 is powered up by applying 5 V to J9 and GND to J11. A differential power supply also may be used to power up the amplifier if common-mode biasing is an issue for DC-coupled applications.
TI ADC SPI Control Interface www.ti.com Figure 5. Found New Hardware 3.2 Setting Up the EVM for ADC SPI Control Users who want to use the ADC SPI interface must configure three jumpers for proper control of the SPI bus. By default, the EVM comes with the ADC configured in parallel mode. In order to use the SPI interface to control the ADC modes of operation, users must: • Move jumper JP12 to short positions 2–3, which places the ADC in serial operation mode.
TI ADC SPI Control Interface www.ti.com Toggle main and advanced page Frequently used registers for power and digital interface This control enables digital features like gain, offset correction and test patterns Select ADC: - ADS41xx - ADS41x2 - ADS41Bxx - ADS58B18 - ADS58B19 Reset the USB IC Summary of current registers being written Manual register write Indication if there is USB communication failure Visual representation of current registers being written Figure 6.
TI ADC SPI Control Interface Change of clock relationship of digital interface www.ti.com Control of offset correction (enabled by disabling low latency mode) Enable different output data as well as a custom pattern Figure 7. GUI Advanced Page 3.4 Controlling the SPI Interface Using TI TSW1200 Software 2.0 The ADS41xxEVM provides an option for the TSW1200 to drive the SPI interface to perform register writes to the ADS41xx register space.
TI ADC SPI Control Interface www.ti.com Figure 8.
Quick Start Setup 4 www.ti.com Quick Start Setup 1. Set up the ADS41xxEVM according the following diagram. • Two signal generators are used and externally locked through the 10-MHz reference. Furthermore, bandpass filters on clock and data input are used to minimize spurs and noise created by the signal generators. Depending on filter attenuation, the clock generator amplitude must be set to 10-13 dBm.
Evaluation www.ti.com 5 Evaluation 5.1 Register Programming Early EVMs (serial number 001 to 050) were assembled with preproduction silicon. To obtain optimum SNR and SFDR performance at input frequencies above 130 MHz, it is recommended to set the following registers: Address Data x03 x04 xD3 x40 xDB xD0 This change is addressed in production silicon. 1 2 6 7 3 4 5 Figure 9. TSW1200 GUI Introduction To 1. 2. 3. 4.
Evaluation 5.2 www.ti.com Quick-Test Results The user can make the jumper setting as mentioned in Table 1. In this configuration, the EVM uses an external clock source from J19 and a direct input signal J6 to the ADC. This setup uses Power Option 2 (Table 3), Clock Option 1 (Table 5), and Analog Input Option 1 (Table 7), which is the default on the EVM. Figure 10 shows the ADC performance capture using TSW1200 with the input signal of a 100-MHz frequency and clock frequency of 245.76 MHz with ADS4149.
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