Datasheet

ADS4126

ADS4129

ADS4146

ADS4149

www.ti.com

SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011

For a positive overload, the D[13:0] output data bits are 3FFFh in offset binary output format and 1FFFh in twos

complement output format. For a negative input overload, the output code is 0000h in offset binary output format

and 2000h in twos complement output format.

Output Data Format

Two output data formats are supported: twos complement and offset binary. They can be selected using the

DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event

of an input voltage overdrive, the digital outputs go to the appropriate full-scale level.

BOARD DESIGN CONSIDERATIONS

Grounding

A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of

the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout

and grounding.

Supply Decoupling

Because the ADS412x/4x already include internal decoupling, minimal external decoupling can be used without

loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum

number of capacitors depends on the actual application. The decoupling capacitors should be placed very close

to the converter supply pins.

Exposed Pad

In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the

digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and

electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and

QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com).

Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149