Datasheet
5010 100 150 200
f - In ueput F eqr ncy M- Hz
IN
f SamplingFrequency- - MSPS
S
SFDR - dBFS
250 300 350 450400 500
80
160
100
120
140
180
200
250
8075706560 85
90
220
240
65
64
72
72
72
72
72
76
76
68
76
76
80
80
80
80
82
82
82
82
84
84
84
84
84
84
84
84
86
86
86
86
86
86
88
88
88
86
88
82
82
ADS4126
,
ADS4129
ADS4146
,
ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain)
Applies to ADS412x and ADS414x
Figure 108.
Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 53
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149