Datasheet

88
87
86
85
84
83
82
81
80
THD(dBc)
25 30
75
InputClockDutyCycle(%)
35 40 5045
74.0
73.5
73.0
72.5
72.0
71.5
71.0
70.5
70.0
SNR(dBFS)
InputFrequency=10MHz
60 7055 65
THD
SNR
1.5
1.0
0.5
0
0.5
1.0
1.5
-
-
-
INL(LSB)
0 2k 4k
16k
OutputCode(LSB)
6k 8k 12k10k 14k
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
-
-
-
-
-
DNL(LSB)
0 2k 4k
16k
OutputCode(LSB)
6k 8k 12k10k 14k
44
40
36
32
28
24
20
16
12
8
4
0
CodeOccurrence(%)
8224
OutputCode(LSB)
RMS=0.999LSB
8226 8228 8230 8232 8234 8236 8238 8225 8227 8229 8231 8233 8235 8237 8239
0.2
1.4
35.7
39.7
12.6
3.8
0.7
6.0
ADS4126 , ADS4129
ADS4146 , ADS4149
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011 www.ti.com
TYPICAL CHARACTERISTICS: ADS4149 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE INTEGRAL NONLINEARITY
Figure 97. Figure 98.
DIFFERENTIAL NONLINEARITY OUTPUT HISTOGRAM WITH INPUTS SHORTED
Figure 99. Figure 100.
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Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149