Datasheet
0
20
40
60
80
100
120
-
-
-
-
-
-
Amplitude(dB)
0 25 50
125
Frequency(MHz)
SFDR=88.3dBc
SNR=72.4dBFS
SINAD=72.2dBFS
THD=84dBc
75
100
0
20
40
60
80
100
120
-
-
-
-
-
-
Amplitude(dB)
0 25 50
125
Frequency(MHz)
75
100
SFDR=87.2dBc
SNR=71.3dBFS
SINAD=71.2dBFS
THD=84.7dBc
0
10
20
30
40
50
60
70
80
90
100
110
120
-
-
-
-
-
-
-
-
-
-
-
-
Amplitude(dB)
0 25 50
125
Frequency(MHz)
75
100
SFDR=78.9dBc
SNR=68.8dBFS
SINAD=68.3dBFS
THD=76.6dBc
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Amplitude(dB)
0 25 50 75 100
125
Frequency(MHz)
EachToneat
7dBFSAmplitude
f =185MHz
f =190MHz
Two-ToneIMD=89.5dBFS
SFDR=95dBFS
-
IN1
IN2
90
86
82
78
74
70
66
SFDR(dBc)
0 50 100 150 200
500
InputFrequency(MHz)
300 400250 350 450
-1dBFSInput,1dBGain
-2dBFSInput,0dBGain
74
73
72
71
70
69
68
67
66
SNR(dBFS)
0 50 100 150 200
500
InputFrequency(MHz)
300 400250 350 450
-1dBFSInput,1dBGain
-2dBFSInput,0dBGain
ADS4126
,
ADS4129
ADS4146
,
ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4149
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
FFT FOR 10MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL
Figure 79. Figure 80.
FFT FOR 300MHz INPUT SIGNAL FFT FOR TWO-TONE INPUT SIGNAL
Figure 81. Figure 82.
SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY
Figure 83. Figure 84.
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