Datasheet
90
88
86
84
82
80
78
76
74
SFDR(dBc)
0.80 0.85
1.10
InputCommon-ModeVoltage(V)
0.90 0.95 1.051.00
75.5
75.0
74.5
74.0
73.5
73.0
72.5
72.0
71.5
SNR(dBFS)
SFDR
SNR
InputFrequency=40MHz
88
87
86
85
84
83
82
81
80
SFDR(dBc)
-40 -15 10
85
Temperature( C)°
35 60
f =40MHz
IN
AVDD=1.7V
AVDD=1.85V
AVDD=1.9V
AVDD=1.8V
AVDD=1.75V
75.0
74.5
74.0
73.5
73.0
72.5
72.0
71.5
71.0
SNR(dBFS)
-40 -15 10
85
Temperature( C)°
35 60
f =40MHz
IN
AVDD=1.7V
AVDD=1.9V
AVDD=1.75V,1.85V
AVDD=1.8V
88
87
86
85
84
83
82
SFDR(dBc)
1.70 1.75 1.80 1.85
1.90
DRVDDSupply(V)
SFDR
SNR
75.5
75.0
74.5
74.0
73.5
73.0
72.5
SNR(dBFS)
f =40MHz
IN
89
88
87
86
85
84
83
SFDR(dBc)
1.70 1.75 1.80 1.85
1.90
DRVDDSupply(V)
SFDR
75.0
74.5
74.0
73.5
73.0
72.5
72.0
SNR(dBFS)
SNR
90
86
82
78
74
70
66
62
58
54
DifferentialClockAmplitude(V )
PP
0.1
SFDR(dBc)
78
76
74
72
70
68
66
64
62
60
SNR(dBFS)
2.3
SFDR(dBc)
SNR(dBFS)
InputFrequency=170MHz
0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1
ADS4126
,
ADS4129
ADS4146
,
ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4146 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
Figure 69. Figure 70.
SNR ACROSS TEMPERATURE vs AVDD SUPPLY PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
Figure 71. Figure 72.
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE
(CMOS) PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE
Figure 73. Figure 74.
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