Datasheet

86
85
84
83
82
81
80
79
78
THD(dBc)
25 30
75
InputClockDutyCycle(%)
35 40 5045
73.0
72.5
72.0
71.5
71.0
70.5
70.0
69.5
69.0
SNR(dBFS)
InputFrequency=10MHz
60 7055 65
THD
SNR
0.3
0.2
0.1
0
0.1
0.2
0.3
-
-
-
INL(LSB)
0 500 1000
4000
OutputCode(LSB)
1500 2000 30002500 3500
0.3
0.2
0.1
0
0.1
0.2
0.3
-
-
-
DNL(LSB)
0 500 1000
4000
OutputCode(LSB)
1500 2000 30002500 3500
ADS4126 , ADS4129
ADS4146 , ADS4149
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011 www.ti.com
TYPICAL CHARACTERISTICS: ADS4129 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE INTEGRAL NONLINEARITY
Figure 54. Figure 55.
DIFFERENTIAL NONLINEARITY
Figure 56.
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Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149