Datasheet
0
20
40
60
80
100
120
-
-
-
-
-
-
Amplitude(dB)
0 25 50
100
Frequency(MHz)
75
125
SFDR=87.7dBc
SNR=70.3dBFS
SINAD=70.2dBFS
THD=83.5dBc
0
20
40
60
80
100
120
-
-
-
-
-
-
Amplitude(dB)
0 25 50
125
Frequency(MHz)
SFDR=87.2dBc
SNR=69.6dBFS
SINAD=69.4dBFS
THD=83.9dBc
75
100
0
20
40
60
80
100
120
-
-
-
-
-
-
Amplitude(dB)
0 25 50
125
Frequency(MHz)
SFDR=79.3dBc
SNR=68dBFS
SINAD=67.5dBFS
THD=76.3dBc
75
100
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Amplitude(dB)
0 25 50 75 100
125
Frequency(GHz)
EachToneat
7dBFSAmplitude
f =185MHz
f =190MHz
Two-ToneIMD=90dBFS
SFDR=94dBFS
-
IN1
IN2
95
90
85
80
75
70
65
60
SFDR(dBc)
0 50 100 150 200
500
InputFrequency(MHz)
300 400250 350 450
-1dBFS ,1dBGainInput
-2dBFS ,0dBGainInput
71.0
70.5
70.0
69.5
69.0
68.5
68.0
67.5
67.0
66.5
66.0
65.5
SNR(dBFS)
0 50 100 150 200
500
InputFrequency(MHz)
300 400250 350 450
-1dBFS ,1dBGainInput
-2dBFS ,0dBGainInput
ADS4126
,
ADS4129
ADS4146
,
ADS4149
www.ti.com
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
TYPICAL CHARACTERISTICS: ADS4129
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
FFT FOR 10MHz INPUT SIGNAL FFT FOR 170MHz INPUT SIGNAL
Figure 36. Figure 37.
FFT FOR 300MHz INPUT SIGNAL FFT FOR TWO-TONE INPUT SIGNAL
Figure 38. Figure 39.
SFDR vs INPUT FREQUENCY SNR vs INPUT FREQUENCY
Figure 40. Figure 41.
Copyright © 2009–2011, Texas Instruments Incorporated Submit Documentation Feedback 39
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149