Datasheet

90
88
86
84
82
80
78
76
74
72
70
68
SFDR(dBc)
0 50 100 150 200
350
InputFrequency(MHz)
300250
71.5
71.0
70.5
70.0
69.5
69.0
68.5
68.0
67.5
67.0
SNR(dBFS)
0 50 100 150 200
350
InputFrequency(MHz)
300250
88
84
80
76
72
68
64
SFDR(dBc)
0 0.5 1.0
6.0
Gain(dB)
1.5 2.0 3.02.5 3.5 5.54.0 4.5 5.0
150MHz
170MHz
220MHz
300MHz
400MHz
500MHz
71
70
69
68
67
66
65
64
63
62
SINAD(dBFS)
0 0.5 1.0
6.0
Gain(dB)
1.5 2.0 3.02.5 3.5 5.54.0 4.5 5.0
150MHz
170MHz
220MHz
300MHz
400MHz
500MHz
105
95
85
75
65
55
45
35
InputAmplitude(dBFS)
-50 0
SFDR(dBc,dBFS)
-40 -30 -20 -10
74
73
72
71
70
69
68
67
SNR(dBFS)
SFDR(dBFS)
SFDR(dBc)
SNR(dBFS)
InputFrequency=40.1MHz
105
95
85
75
65
55
45
35
InputAmplitude(dBFS)
-50 0
SFDR(dBc,dBFS)
-40 -30 -20 -10
74
73
72
71
70
69
68
67
SNR(dBFS)
SFDR(dBFS)
SFDR(dBc)
SNR(dBFS)
InputFrequency=170.1MHz
ADS4126 , ADS4129
ADS4146 , ADS4149
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011 www.ti.com
TYPICAL CHARACTERISTICS: ADS4126 (continued)
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5V
PP
differential clock
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.
SFDR vs INPUT FREQUENCY (CMOS) SNR vs INPUT FREQUENCY (CMOS)
Figure 21. Figure 22.
SFDR ACROSS GAIN AND INPUT FREQUENCY SINAD ACROSS GAIN AND INPUT FREQUENCY
Figure 23. Figure 24.
PERFORMANCE ACROSS INPUT AMPLITUDE (Single PERFORMANCE ACROSS INPUT AMPLITUDE (Single
Tone) Tone)
Figure 25. Figure 26.
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Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149