Datasheet

PowerSupply
AVDD,DRVDD
RESET
SEN
t
1
t
2
t
3
ADS4126 , ADS4129
ADS4146 , ADS4149
www.ti.com SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
RESET TIMING CHARACTERISTICS
NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 14. Reset Timing Diagram
RESET TIMING REQUIREMENTS
Typical values at +25°C and minimum and maximum values across the full temperature range: T
MIN
= –40°C to T
MAX
= +85°C,
unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Delay from power-up of AVDD and DRVDD to RESET
t
1
Power-on delay 1 ms
pulse active
10 ns
Pulse width of active RESET signal that resets the
t
2
Reset pulse width
serial registers
1
(1)
µs
t
3
Delay from RESET disable to SEN active 100 ns
(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µs, the device could
enter the parallel configuration mode briefly and then return back to serial interface mode.
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