Datasheet

AVDD

(5/8)AVDD

(3/8)AVDD

(5/8)AVDD

AVDDGND

ToParallelPin

ADS4126

ADS4129

ADS4146

ADS4149

SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011

www.ti.com

DEVICE CONFIGURATION

The ADS412x/4x have several modes that can be configured using a serial programming interface, as described

in Table 7, Table 8, and Table 9. In addition, the devices have two dedicated parallel pins for quickly configuring

commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The

analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).

Table 7. DFS: Analog Control Pin

DESCRIPTION

VOLTAGE APPLIED ON DFS (Data Format/Output Interface)

0, +100mV/–0mV Twos complement/DDR LVDS

(3/8) AVDD ± 100mV Twos complement/parallel CMOS

(5/8) AVDD ± 100mV Offset binary/parallel CMOS

AVDD, +0mV/–100mV Offset binary/DDR LVDS

Table 8. OE: Digital Control Pin

VOLTAGE APPLIED ON OE DESCRIPTION

0 Output data buffers disabled

AVDD Output data buffers enabled

When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device

in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have

any alternative functions. Keep SEN tied high and SCLK tied low on the board.

Table 9. SDATA: Digital Control Pin

VOLTAGE APPLIED ON SDATA DESCRIPTION

0 Normal operation

Logic high Device enters standby

Figure 11. Simplified Diagram to Configure DFS Pin

Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149