Datasheet

O
E
O
E
O
E
O
E
O
EE
O
E
O
E
O
E
O
E
O
N+1 N+2
InputClock
CLKOUTM
CLKOUTP
OutputData
(2)
(DXP,DXM)
DDRLVDS
N 1- N N+1
CLKOUT
OutputData
ParallelCMOS
InputSignal
SampleN
N+1
N+2
N+3 N+4
N+10
N+11
N+12
t
A
t
SU
t
SU
t
H
t
H
t
PDI
t
PDI
CLKP
CLKM
N 10- N 9- N 8- N 7-
N 10- N 9- N 8-
N 7-
N 6-
10ClockCycles
(1)
N
10ClockCycles
(1)
ADS4126 , ADS4129
ADS4146 , ADS4149
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011 www.ti.com
Table 6. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)
TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK
t
START
(ns) t
DV
(ns)
SAMPLING FREQUENCY
(MSPS) MIN TYP MAX MIN TYP MAX
250 1.6 2.5 3.2
230 1.1 2.9 3.5
200 0.3 3.5 4.2
185 0 3.9 4.5
170 –1.3 4.3 5
(1) ADC latency in low-latency mode. At higher sampling frequencies, t
DPI
is greater than one clock cycle which then makes the overall
latency = ADC latency + 1.
(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).
Figure 8. Latency Diagram
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