Datasheet

Dn_Dn+1_P
Dn_Dn+1_M
GND
Logic0
V
ODL
Logic1
V
ODH
V
OCM
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www.ti.com SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
TIMING CHARACTERISTICS
(1) With external 100Ω termination.
Figure 7. LVDS Output Voltage Levels
TIMING REQUIREMENTS: LVDS and CMOS Modes
(1)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock,
C
LOAD
= 5pF
(2)
, and R
LOAD
= 100Ω
(3)
, unless otherwise noted. Minimum and maximum values are across the full temperature
range: T
MIN
= –40°C to T
MAX
= +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER CONDITIONS MIN TYP MAX UNIT
t
A
Aperture delay 0.6 0.8 1.2 ns
Variation of aperture Between two devices at the same temperature and
±100 ps
delay DRVDD supply
t
J
Aperture jitter 100 f
S
rms
Time to valid data after coming out of STANDBY
5 25 µs
mode
Wakeup time
Time to valid data after coming out of PDN GLOBAL
100 500 µs
mode
Clock
Low-latency mode (default after reset) 10
cycles
Low-latency mode disabled (gain enabled, offset Clock
ADC latency
(4)
16
correction disabled) cycles
Low-latency mode disabled (gain and offset Clock
17
correction enabled) cycles
DDR LVDS MODE
(5)(6)
t
SU
Data setup time
(3)
Data valid
(7)
to zero-crossing of CLKOUTP 0.75 1.1 ns
Zero-crossing of CLKOUTP to data becoming
t
H
Data hold time
(3)
0.35 0.6 ns
invalid
(7)
Input clock rising edge cross-over to output clock
Clock propagation
t
PDI
rising edge cross-over 3 4.2 5.4 ns
delay
1MSPS ≤ sampling frequency ≤ 250MSPS
Between two devices at the same temperature and
Variation of t
PDI
±0.6 ns
DRVDD supply
(1) Timing parameters are ensured by design and characterization but are not production tested.
(2) C
LOAD
is the effective external single-ended load capacitance between each output pin and ground.
(3) R
LOAD
is the differential load resistance between the LVDS output pair.
(4) At higher frequencies, t
PDI
is greater than one clock period and overall latency = ADC latency + 1.
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
(6) The LVDS timings are unchanged for low latency disabled and enabled.
(7) Data valid refers to a logic high of 1.26V and a logic low of 0.54V.
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