Datasheet
36
35
34
33
32
31
30
29
28
27
26
25
DRGND
DRVDD
D1
D0
NC
NC
RESET
SCLK
SDATA
SEN
AVDD
AGND
D13
VCM
D12
AGND
D11
INP
D10
INM
D9
AGND
D8
AVDD
D7
AGND
D6
AVDD
D5
NC
D4
AVDD
D3
RESERVED
D2
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
DRGND
DRVDD
OVR_SDOUT
UNUSED
CLKOUT
DFS
OE
AVDD
AGND
CLKP
CLKM
AGND
48 47 46 45 44 43 42
41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
ADS4126
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ADS4129
ADS4146
,
ADS4149
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SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
RGZ PACKAGE
(4)
QFN-48
(TOP VIEW)
(4) The PowerPAD is connected to DRGND.
Figure 4. ADS414x CMOS Pinout
ADS412x, ADS414x Pin Assignments (CMOS Mode)
# OF
PIN NAME PIN NUMBER PINS FUNCTION DESCRIPTION
AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply
AGND 9, 12, 14, 17, 19, 25 6 I Analog ground
CLKP 10 1 I Differential clock input, positive
CLKM 11 1 I Differential clock input, negative
INP 15 1 I Differential analog input, positive
INM 16 1 I Differential analog input, negative
Outputs the common-mode voltage (0.95V) that can be used externally to bias the
VCM 13 1 O
analog input pins.
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through
hardware RESET by applying a high pulse on this pin or by using the software reset
RESET 30 1 I option; refer to the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this
condition, SEN can be used as an analog control pin.
RESET has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. When RESET is
SCLK 29 1 I high, SCLK has no function and should be tied to ground. This pin has an internal
180kΩ pull-down resistor.
This pin functions as a serial interface data input when RESET is low. When RESET is
SDATA 28 1 I high, SDATA functions as a STANDBY control pin (see Table 9). This pin has an
internal 180kΩ pull-down resistor.
This pin functions as a serial interface enable input when RESET is low. When RESET
SEN 27 1 I is high, SEN has no function and should be tied to AVDD. This pin has an internal
180kΩ pull-up resistor to AVDD.
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to
OE 7 1 I
DRVDD.
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