Datasheet

ADS4126 , ADS4129
ADS4146 , ADS4149
www.ti.com SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
ADS412x, ADS414x Pin Assignments (LVDS Mode) (continued)
# OF
PIN NAME PIN NUMBER PINS FUNCTION DESCRIPTION
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to
OE 7 1 I
DRVDD.
Data format select input. This pin sets the DATA FORMAT (twos complement or offset
DFS 6 1 I
binary) and the LVDS/CMOS output interface type. See Table 7 for detailed information.
RESERVED 23 1 I Digital control pin, reserved for future use
CLKOUTP 5 1 O Differential output clock, true
CLKOUTM 4 1 O Differential output clock, complement
Refer to Figure 1 and
D0_D1_P 1 O Differential output data D0 and D1 multiplexed, true
Figure 2
Refer to Figure 1 and
D0_D1_M 1 O Differential output data D0 and D1 multiplexed, complement
Figure 2
Refer to Figure 1 and
D2_D3_P 1 O Differential output data D2 and D3 multiplexed, true
Figure 2
Refer to Figure 1 and
D2_D3_M 1 O Differential output data D2 and D3 multiplexed, complement
Figure 2
Refer to Figure 1 and
D4_D5_P 1 O Differential output data D4 and D5 multiplexed, true
Figure 2
Refer to Figure 1 and
D4_D5_M 1 O Differential output data D4 and D5 multiplexed, complement
Figure 2
Refer to Figure 1 and
D6_D7_P 1 O Differential output data D6 and D7 multiplexed, true
Figure 2
Refer to Figure 1 and
D6_D7_M 1 O Differential output data D6 and D7 multiplexed, complement
Figure 2
Refer to Figure 1 and
D8_D9_P 1 O Differential output data D8 and D9 multiplexed, true
Figure 2
Refer to Figure 1 and
D8_D9_M 1 O Differential output data D8 and D9 multiplexed, complement
Figure 2
Refer to Figure 1 and
D10_D11_P 1 O Differential output data D10 and D11 multiplexed, true
Figure 2
Refer to Figure 1 and
D10_D11_M 1 O Differential output data D10 and D11 multiplexed, complement
Figure 2
Refer to Figure 1 and
D12_D13_P 1 O Differential output data D12 and D13 multiplexed, true
Figure 2
Refer to Figure 1 and
D12_D13_M 1 O Differential output data D12 and D13 multiplexed, complement
Figure 2
This pin functions as an out-of-range indicator after reset, when register bit
OVR_SDOUT 3 1 O
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.
DRVDD 2, 35 2 I 1.8V digital and output buffer supply
DRGND 1, 36, PAD 2 I Digital and output buffer ground
Refer to Figure 1 and
NC — — Do not connect
Figure 2
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