Datasheet
36
35
34
33
32
31
30
29
28
27
26
25
DRGND
DRVDD
D0_D1_P
D0_D1_M
NC
NC
RESET
SCLK
SDATA
SEN
AVDD
AGND
D12_D13_P
VCM
D12_D13_M
AGND
D10_D11_P
INP
D10_D11_M
INM
D8_D9_P
AGND
D8_D9_M
AVDD
D6_D7_P
AGND
D6_D7_M
AVDD
D4_D5_P
NC
D4_D5_M
AVDD
D2_D3_P
RESERVED
D2_D3_M
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
DRGND
DRVDD
OVR_SDOUT
CLKOUTM
CLKOUTP
DFS
OE
AVDD
AGND
CLKP
CLKM
AGND
48 47 46 45 44 43 42
41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
ADS4126
,
ADS4129
ADS4146
,
ADS4149
SBAS483G – NOVEMBER 2009–REVISED JANUARY 2011
www.ti.com
RGZ PACKAGE
(2)
QFN-48
(TOP VIEW)
(2) The PowerPAD™ is connected to DRGND.
Figure 2. ADS414x LVDS Pinout
ADS412x, ADS414x Pin Assignments (LVDS Mode)
# OF
PIN NAME PIN NUMBER PINS FUNCTION DESCRIPTION
AVDD 8, 18, 20, 22, 24, 26 6 I 1.8V analog power supply
AGND 9, 12, 14, 17, 19, 25 6 I Analog ground
CLKP 10 1 I Differential clock input, positive
CLKM 11 1 I Differential clock input, negative
INP 15 1 I Differential analog input, positive
INM 16 1 I Differential analog input, negative
Outputs the common-mode voltage (0.95V) that can be used externally to bias the
VCM 13 1 O
analog input pins.
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through
hardware RESET by applying a high pulse on this pin or by using the software reset
RESET 30 1 I option; refer to the Serial Interface section.
When RESET is tied high, the internal registers are reset to the default values. In this
condition, SEN can be used as an analog control pin.
RESET has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. When RESET is
SCLK 29 1 I high, SCLK has no function and should be tied to ground. This pin has an internal
180kΩ pull-down resistor.
This pin functions as a serial interface data input when RESET is low. When RESET is
SDATA 28 1 I high, SDATA functions as a STANDBY control pin (see Table 9). This pin has an
internal 180kΩ pull-down resistor.
This pin functions as a serial interface enable input when RESET is low. When RESET
SEN 27 1 I is high, SEN has no function and should be tied to AVDD. This pin has an internal
180kΩ pull-up resistor to AVDD.
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