Datasheet

CLK
DRDY
t
SCLK
SCLK
external
t
DRPW
t
CLKDR
t
CSSC
t
CSFDO
t
SPW
t
SPW
t
DOPD
t
CSRDO
DOUT
CS
(1)
MSB
LSB
t
CLK
t
SCLKDR
Hi-Z
START
DRDY
CLK
t
SETTLE
t
START_CLKR
t
CLKDR
t
START
ADS1672
SBAS402D JUNE 2008REVISED JULY 2010
www.ti.com
(1) CS may be tied low.
Figure 2. Data Retrieval Timing with External SCLK (SCLK_SEL = 1)
TIMING REQUIREMENTS: External SCLK
At T
A
= –40°C to +85°C, and DVDD = 2.7V to 3.3V.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
CLK
CLK period (1/f
CLK
) 50 ns
t
CLKDR
CLK to DRDY delay 37 ns
t
DRPW
DRDY pulse width 1 t
CLK
t
CSSC
CS active low to first Shift Clock (setup time) 5 ns
t
SCLK
SCLK period (1/f
SCLK
) 25 ns
t
SPW
SCLK high or low pulse width 12 ns
t
DOPD
Rising edge of SCLK to new valid data output (propagation delay) 11 ns
t
SCLKDR
Setup time of DRDY rising after SCLK falling edge 3 t
CLK
t
CRSDO
CS inactive to data output 3-state 8 ns
Figure 3. START Timing
TIMING REQUIREMENTS: START
At T
A
= –40°C to +85°C, and DVDD = 2.7V to 3.3V.
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
START_CLKR
Setup time, rising edge of START to rising edge of CLK 0.5 t
CLK
t
START
Start pulse width 1 t
CLK
8 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS1672