Datasheet
ADS1672
SBAS402D –JUNE 2008–REVISED JULY 2010
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Table 1. TERMINAL FUNCTIONS (continued)
PIN
NAME NO. FUNCTION DESCRIPTION
Configure low-latency digital filter.
LL_CONFIG 32 Digital Input If LL_CONFIG = '0', then single-cycle settling is selected.
If LL_CONFIG = '1', then fast-response is selected.
Digital filter path selection.
FPATH 33 Digital Input If FPATH = '0', then path is wide-bandwidth.
If FPATH = '1', then path is low-latency.
DRATE[1:0] 35, 36 Digital Input Data rate selection
START 37 Digital Input Start convert, reset, and synchronization control input
CS 38 Digital Input Chip select; active low.
OTRD 39 Digital Output Digital filter out-of-range indicator
RSV3 40 Reserved This pin must be left floating. Do not connect or short to ground.
Negative shift clock output.
SCLK 41 Digital Output If SCLK_SEL = '0', then SCLK is the complementary shift clock output.
If SCLK_SEL = '1', then SCLK always output is 3-state.
Positive shift clock output.
SCLK 42 Digital Input/Output If SCLK_SEL = '0', then SCLK is an output.
If SCLK_SEL = '1', then SCLK is an input.
DOUT 43 Digital Output Negative LVDS serial data output
DOUT 44 Digital Output Positive LVDS serial data output
DRDY 45 Digital Output Negative data ready output
DRDY 46 Digital Output Positive data ready output
CLK 55 Digital Input Master clock input
CAP1 59 Analog Terminal for 1mF external bypass capacitor
VREFN 60, 61 Analog Negative reference voltage. Short to analog ground.
CAP2 62 Analog Terminal for 1mF external bypass capacitor
VREFP 63, 64 Analog Positive reference voltage
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