Datasheet

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DVDD
DGND
DRDY
DRDY
DOUT
DOUT
SCLK
SCLK
RSV3
OTRD
CS
START
DRATE[0]
DRATE[1]
DVDD
FPATH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AVDD
AGND
AGND
AINN
AINP
AGND
AVDD
RBIAS
AGND
AGND
AVDD
AVDD
VCM
DGND
DGND
DGND
VREFP
VREFP
CAP2
VREFN
VREFN
CAP1
AVDD
AGND
AGND
CLK
AGND
AVDD
DVDD
DGND
DGND
DVDD
DGND
DGND
DGND
DGND
RSV2
RSV1
DVDD
DVDD
DGND
DGND
DVDD
PDWN
SCLK_SEL
LVDS
DGND
LL_CONFIG
64 63 62 61 60 59 58 57 56 55 54
17 18 19 20 21 22 23 24 25 26 27
53 52 51 50 49
28 29 30 31 32
ADS1672
ADS1672
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SBAS402D JUNE 2008REVISED JULY 2010
DEVICE INFORMATION
TQFP PACKAGE
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
PIN
NAME NO. FUNCTION DESCRIPTION
1, 7, 11, 12, 53,
AVDD Analog Analog supply
58
2, 3, 6, 9, 10,
AGND Analog Analog ground
54, 56, 57
AINN 4 Analog Input Negative analog input
AINP 5 Analog Input Positive analog input
RBIAS 8 Analog Analog bias setting resistor
VCM 13 Analog Terminal for external bypass capacitor connection to internal common-mode voltage
14, 15, 16, 17,
18, 19, 20, 25,
DGND Digital Digital ground
26, 31, 47, 50,
51
RSV2 21 Reserved Short to digital ground
RSV1 22 Reserved Short to digital ground
23, 24, 27, 34,
DVDD Digital Digital supply
48, 49, 52
PDWN 28 Digital Input Power-down control, active low
Shift-clock source select.
SCLK_SEL 29 Digital Input If SCLK_SEL = '0', then SCLK is internally generated.
If SCLK_SEL = '1', then SCLK must be externally generated.
Serial interface select.
LVDS 30 Digital Input If LVDS = '0', then interface is LVDS-compatible.
If LVDS = '1', then interface is CMOS-compatible.
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