Datasheet
R
BIAS
RBIAS
AGND
ADS1672
START
1
ADS1672
1
CLK
DRDY DRDY
1
START
CLK
START
2
ADS1672
2
CLK
DRDY DRDY
2
START
CLK
DRDY
1
DRDY
2
t
SETTLE
ADS1672
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SBAS402D –JUNE 2008–REVISED JULY 2010
SYNCHRONIZING MULTIPLE ADS1672s ANALOG POWER DISSIPATION
The START pin should be applied at power-up and An external resistor connected between the RBIAS
resets the ADS1672 filters. START begins the pin and the analog ground sets the analog current
conversion process, and the START pin enables level, as shown in Figure 37. The current is inversely
simultaneous sampling with multiple ADS1672s in proportional to the resistor value. Figure 18 and
multichannel systems. All devices to be synchronized Figure 20 (in the Typical Characteristics) show power
must use a common CLK input. and typical performance at values of R
BIAS
for
different CLK frequencies. Notice that the analog
It is recommended that the START pin be aligned to
current can be reduced when using a slower
the falling edge of CLK to ensure proper
frequency CLK input because the modulator has
synchronization because the START signal is
more time to settle. Avoid adding any capacitance in
internally latched by the ADS1672 on the rising edge
parallel to R
BIAS
, because this additional capacitance
of CLK.
interferes with the internal circuitry used to set the
biasing.
With the CLK inputs running, pulse START on the
falling edge of CLK, as shown in Figure 36.
Afterwards, the converters operate synchronously
with the DRDY outputs updating simultaneously. After
synchronization, DRDY is held high until the digital
filter has fully settled.
Figure 37. External Resistor Used to Set Analog
Power Dissipation (Depends on f
CLK
)
POWER DOWN (PDWN)
When not in use, the ADS1672 can be powered down
by taking the PDWN pin low. All circuitry shuts down,
including the voltage reference. To minimize the
digital current during power down, stop the clock
signal supplied to the CLK input. Make sure to allow
time for the reference to start up after exiting
power-down mode.
After the reference has stabilized, allow for the
modulator and digital filter to settle before retrieving
data.
Figure 36. Synchronizing Multiple Converters
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