Datasheet

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2 1
REF
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-V
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REF
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-V
REF
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ADS1672
SBAS402D JUNE 2008REVISED JULY 2010
www.ti.com
SERIAL SHIFT CLOCK (SCLK, SCLK, exceeding full-scale. Table 9 summarizes the ideal
SCLK_SEL) output codes for different input signals. When the
input is positive out-of-range, exceeding the positive
The serial shift clock SCLK is used to shift out the
full-scale value of V
REF
, the output clips to all
conversion data, MSB first, onto the Data Output
7FFFFFh. Likewise, when the input is negative
pins. Either an internally- or externally-generated shift
out-of-range by going below the negative full-scale
clock can be selected using the SCLK_SEL pin. If
value of –V
REF
, the output clips to 800000h.
SCLK_SEL is set to '0', a free-running shift clock is
generated internally from the master clock and
Table 9. Ideal Output Code vs Input Signal
outputs on the SCLK and SCLK pins. The LVDS pin
INPUT SIGNAL
determines if the output voltages are CMOS or LVDS.
V
IN
= (AINP – AINN) IDEAL OUTPUT CODE
(1)
If SCLK_SEL is set to '1' and LVDS is set to '1', the
V
REF
7FFFFFh
SCLK pin is configured as an input to accept an
externally-generated shift clock. In this case, the
000001h
SCLK pin always outputs low. When SCLK_SEL is
set to '0', the SCLK and SCLK pins are configured as
0 000000h
outputs, and the shift clock is generated internally
using the master clock input (CLK).
FFFFFFh
When LVDS signal swings are used, the shift clock is
automatically generated internally regardless of the
state of SCLK_SEL. In this case, SCLK_SEL cannot
8000000h
be left floating; it must be tied high or low.
(1) Excludes effects of noise, INL, offset and gain errors.
Table 8 summarizes the ADS1672 supported serial
clock configurations.
CLOCK INPUT (CLK)
Table 8. Supported Serial Clock Configurations
The ADS1672 requires that an external clock signal
DIGITAL OUTPUTS SHIFT CLOCK (SCLK)
be applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with
LVDS Must be generated internally
any high-speed data converter, a high-quality clock is
Internal (SCLK_SEL = '0')
CMOS
essential for optimum performance. Crystal clock
External (SCLK_SEL = '1')
oscillators are the recommended CLK source; other
sources, such as frequency synthesizers, are usually
CHIP SELECT (CS)
inadequate. Make sure to avoid excess ringing on the
CLK input; keep the trace as short as possible.
The chip select input (CS) allows multiple devices to
share a serial bus. When CS is inactive (high), the
Measuring high-frequency, large amplitude signals
serial interface is reset and the data output pins
requires tight control of clock jitter. The uncertainty
DOUT and DOUT enter a high-impedance state.
during sampling of the input from clock jitter limits the
SCLK is internally generated; the SCLK and SCLK
maximum achievable SNR. This effect becomes more
output pins also enter a high-impedance state when
pronounced with higher frequency and larger
CS is inactive. The DRDY and DRDY outputs are
magnitude inputs. Fortunately, the ADS1672
always active, regardless of the state of the CS
oversampling topology reduces clock jitter sensitivity
output. CS may be permanently tied low when the
over that of Nyquist rate converters, such as pipeline
outputs do not share a bus.
and successive approximation converters, by at least
a factor of 32.
DATA FORMAT
For best performance, the duty cycle of CLK should
The ADS1672 outputs 24 bits of data in two’s
be very close to 50%. The rise and fall times of the
complement format. A positive full-scale input
clock should be less than 2ns and the clock
produces an output code of 7FFFFFh, and the
amplitude should be equal to AVDD.
negative full-scale input produces an output code of
800000h. The output clips at these codes for signals
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