Datasheet

ADS1672
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SBAS402D JUNE 2008REVISED JULY 2010
OTRD FUNCTION When using LVDS, the CS function is not available
and SCLK must be internally generated. The states of
The ADS1672 provides an out-of-range (OTRD) pin
the CS and SCLK_SEL pins are ignored, but do not
that can be used in feedback loops to set the
leave these pins floating; they must be tied high or
dynamic range of the input signal.
low.
The OTRD function is triggered when the output code
of the digital filter exceeds the positive or negative USING CMOS OUTPUT SWINGS
full-scale range. OTRD goes high on the rising edge
When the LVDS pin is set to '1', the ADS1672
of DRDY. When the digital output code returns within
outputs are CMOS-compliant and swing from rail to
the full-scale range, OTRD returns low on the next
rail. The data out and data ready signals are output
rising edge of DRDY. OTRD can also be used when
on the differential pairs of pins DOUT/DOUT and
small out-of-range input glitches must be ignored.
DRDY/DRDY, respectively. Note that these are the
same pins used to output LVDS signals when the
SERIAL INTERFACE
LVDS pin is set to '0'. DOUT and DRDY are
complementary outputs provided for convenience.
The ADS1672 offers a flexible and easy-to-use,
When not in use, these pins should be left floating.
read-only serial interface designed to connect to a
wide range of digital processors, including DSPs,
See the Serial Shift Clock section for a description of
microcontrollers, and FPGAs. The ADS1672 serial
the SCLK and SCLK pins.
interface can be configured to support either standard
CMOS voltage swings or low-voltage differential
DATA OUTPUT (DOUT, DOUT)
swings (LVDS). In addition, when using standard
CMOS voltage swings, SCLK can be internally or
Data are output serially from the ADS1672, MSB first,
externally generated.
on the DOUT and DOUT pins. When LVDS signal
swings are used, these two pins act as a differential
The ADS1672 is entirely controlled by pins; there are
pair to produce the LVDS-compatible differential
no registers to program. Connect the I/O pins to the
output signal. When CMOS signal swings are used,
appropriate level to set the desired function.
the DOUT pin is the complement of DOUT. If DOUT
Whenever changing the I/O pins that are used to
is not used, it should be left floating.
control the ADS1672, be sure to issue a START
pulse immediately after the change in order to latch
DATA READY (DRDY, DRDY)
the new values.
Data ready for retrieval are indicated on the DRDY
USING LVDS OUTPUT SWINGS
and DRDY pins. When LVDS signal swings are used,
these two pins act as a differential pair to produce the
When the LVDS pin is set to '0', the ADS1672
LVDS-compatible differential output signal. When
outputs are LVDS TIA/EIA-644A compliant. The data
CMOS signal swings are used, the DRDY pin is the
out, shift clock, and data ready signals are output on
complement of DRDY. If one of the data ready pins is
the differential pairs of pins DOUT/DOUT,
not used when CMOS swings are selected, it should
SCLK/SCLK, and DRDY/DRDY, respectively. The
be left floating.
voltage on the outputs is centered on 1.2V and
swings approximately 350mV differentially. For more
information on the LVDS interface, refer to the
document Low-Voltage Differential Signaling (LVDS)
Design Notes (literature number SLLA014) available
for download at www.ti.com.
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