Datasheet

0
10
20
30
40
50
60
-
-
-
-
-
-
-
-
70
80
Magnitude(dB)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Frequency(f /f )
IN DATA
DRATE[1:0]= 00
DRATE[1:0]= 11
120
100
80
60
40
20
0
Settling(%)
0
1 2
3
4
Conversions(1/f )
DRDY-FR
0
20
40
60
80
100
120
-
-
-
-
-
-
-140
Magnitude(dB)
0
1 2
Frequency(f /f )
IN CLK
3
Data1 Data2
Data3
Data4
Data0
V
IN
DRDY
LL-FR
Changeon
AnalogInputs
Fully-Settled
DataAvailable
ADS1672
SBAS402D JUNE 2008REVISED JULY 2010
www.ti.com
It is important to note, however, that the absolute
settling time of the low-latency path does not change
when using the fast response configuration. Changes
on the input signal during conversions after the initial
settling require multiple cycles to fully settle. To help
illustrate this requirement, consider a change on the
inputs as shown in Figure 29, where START is
assumed to have been taken high before the input
voltage was changed.
The readings after the input change settle as shown
in Figure 26. Conversion 3 provides a fully-settled
result at the new V
IN
signal.
Figure 27. Frequency Response of Low-Latency
Filter in Fast-Response Configuration
Figure 26. Step Response for Low-Latency Filter
with Fast-Response Configuration
Frequency Response
Figure 27 shows the frequency response for the
Figure 28. Extended Frequency Response of
low-latency filter path normalized to the output data
Low-Latency Path
rate, f
DATA
. The overall frequency response repeats at
the modulator sampling rate, which is the same as
the input clock frequency. Figure 28 shows the
response with the fastest data rate selected
(625kSPS when f
CLK
= 20MHz).
NOTE: START pin held high previous to change on analog inputs.
Figure 29. Settling Example with the Low-Latency Filter in Fast-Response Configuration
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