Datasheet
t
SETTLE-LL
t
DRDY-FR
t
DRDY-SCS SETTLE-LL
=t
START
CLK
t
START_CLKR
t
CLKDR
DRDY
SCS
DRDY
FR
ADS1672
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SBAS402D –JUNE 2008–REVISED JULY 2010
The second configuration is fast response. The Figure 25 illustrates the response of both
DRATE[1:0] digital input pins select the data rate for configurations on approximately the same time scale
the Fast Response Configuration, as shown in in order to highlight the differences. With the
Table 6. When selected, this configuration provides a single-cycle settling configuration, each conversion
higher output data rate. The faster output data rate fully settles; in other words, the conversion period
allows for more averaging by a post-processor within t
DRDY-SCS
= t
SETTLE-LL
. The benefit of this configuration
a given time interval to reduce noise. It also provides is its simplicity—the ADS1672 functions similar to a
a faster indication of changes on the inputs when SAR converter and there is no need to consider
monitoring quickly-changing signals (for example, in a discarding partially-settled data because each
control loop application). conversion is fully settled.
With the fast response configuration, the data rate for
Table 6. Low-Latency Data Rates with
conversions after initial settling is faster; that is, the
Fast-Response Configuration
conversion time is less than the settling:
DRATE DATA RATE SETTLING TIME, –3dB
t
DRDY-FR
< t
SETTLE-LL
. One benefit of this configuration
[1:0] (1/t
DRDY-FR
) t
SETTLE-LL
BANDWIDTH
is a faster response to changes on the inputs,
00 78.125kSPS 27.55ms 550 t
CLK
34kHz
because data are supplied at a faster rate. Another
01 156.25kSPS 14.75ms 294 t
CLK
68kHZ advantage is better support for post-processing. For
example, if multiple readings are averaged to reduce
10 312.5kSPS 8.35ms 166 t
CLK
130kHZ
noise, the higher data rate of the fast response
11 625kSPS 5.55ms 110 t
CLK
215kHz
configuration allows this averaging to happen in less
time than it requires with the single-cycle settling
Settling Time
filter. A third benefit is the ability to measure higher
input frequencies without aliasing as a result of the
The settling time in absolute time (ms) is the same for
higher data rate.
both configurations of the low-latency filter, as shown
in Table 5 and Table 6. The difference between the
configurations is seen with the timing of the
conversions after the filter has settled from a pulse on
the START pin.
NOTE: DRDY
SCS
is the DRDY output with the low-latency single-cycle settling configuration. DRDY
FR
is the DRDY output with the
low-latency fast-response settling configuration.
Figure 25. Low-Latency Single-Cycle Settling and Fast-Response Configuration Conversion Timing
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