Datasheet
ADS1672
SBAS402D –JUNE 2008–REVISED JULY 2010
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DIGITAL FILTER LOW-LATENCY DIGITAL FILTER
In delta-sigma ADCs, the digital filter has a critical The low-latency (LL) filter provides a fast settling
influence on device performance. The digital filter response targeted for applications that need
sets the frequency response, data rate, bandwidth, high-precision measurements with minimal latency. A
and settling time. Choosing to optimize some of these good example of this type of application is using a
features in a filter means that compromises must be multiplexer to measure multiple inputs. The faster that
made with other specifications. These tradeoffs the ADC settles, the faster the measurement can
determine the applications for which the device is complete and the multiplexer can advance to the next
best suited. input.
The ADS1672 offers two digital filters on-chip, and The ADS1672 LL filter supports two configurations to
allows the user to direct the output data from the help optimize performance for these types of
modulator to either the Wide-Bandwidth or applications.
Low-Latency filter. These filters allow the user to use
The LL_CONFIG input pin selects the configuration,
one converter design to address multiple applications.
as shown in Table 4. Be sure to strobe the START
The Low-Latency path filter has minimal latency or
pin after changing the configuration. If a conversion is
settling time. This path is ideal for measurements with
in process during a configuration change, the output
large, quick changes on the inputs (for example,
data for that conversion are not valid and should be
when using a multiplexer). The low-latency
discarded.
characteristic allows the user to cycle through the
multiplexer at high speeds. The frequency
Table 4. Low-Latency Pin Configurations
characteristics are relaxed in order to provide the low
LOW-LATENCY
latency.
LL_CONFIG PIN CONFIGURATION
The other path provides a filter with excellent
0 Single-cycle settling
frequency response characteristics. The passband
1 Fast response
ripple is extremely small, the transition band is very
steep, and there is large stop band attenuation.
The first configuration is single-cycle settling. As the
These characteristics are needed for high-resolution
name implies, this configuration allows for the filter to
measurements of ac signals. The tradeoff here is that
completely settle in one conversion cycle; there is no
settling time increases; but for signal processing, this
need to discard data. Each data output is comprised
increase is not generally a critical concern.
of information taken during only the previous
conversion. The DRATE[1:0] digital input pins select
The FPATH digital input pin sets the filter path
the data rate for the Single-Cycle Settling
selection, as shown in Table 3. Note that the START
configuration, as shown in Table 5. Note that the
pin must be strobed after a change to the filter path
START pin must be strobed after a change to the
selection or data rate. If a conversion is in process
data rate. If a conversion is in process during a data
during a filter path or data rate change, the output
rate change, the output data for that conversion are
data are not valid and should be discarded.
not valid and should be discarded.
Table 3. ADS1672 Filter Path Selection
blank
FPATH PIN SELECTED FILTER PATH
blank
1 Low-latency path
0 Wide-bandwidth path
Table 5. Low-Latency Data Rates with Single-Cycle Settling Configuration
DRATE[1:0] DATA RATE (1/t
DRDY-SCS
) SETTLING TIME, t
SETTLE-LL
–3dB BANDWIDTH
(1)
00 36.30kSPS 27.55ms 550 t
CLK
34kHz
01 67.80kSPS 14.75ms 294 t
CLK
68kHZ
10 119.76kSPS 8.35ms 166 t
CLK
130kHZ
11 180.18kSPS 5.55ms 110 t
CLK
215kHz
(1) The input signal aliases when its frequency exceeds f
DATA
/2, in accordance with the Nyquist theorem.
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