Datasheet
Biasing
RBIAS
CAP1
CAP2
AINP
AINN
VCM
CS
LVDS
OTRD
FPATH
DRATE[1:0]
LL_CONFIG
ADS1672
SCLK_SEL
DS
Modulator
DVDD
DGND
AGND
AVDD
VREFP
VREFN
Dual
Path
Filter
Low-LatencyFilter
Wide-BandwidthFilter
CMOS-and
LVDS-
Compatible
Serial
Interface
and
Control
V
IN
V
REF
SCLK, SCLK
DOUT, DOUT
DRDY, DRDY
CLK
START
PDWN
S
S
ADS1672
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SBAS402D –JUNE 2008–REVISED JULY 2010
OVERVIEW
The ADS1672 is a 24-bit, ΔΣ analog-to-digital A dedicated START pin allows precise conversion
converter (ADC). It provides high-resolution control; toggle the pin to begin the conversion
measurements of both ac and dc signals and features process. The ADS1672 is configured by setting the
an advanced multi-stage analog modulator with a appropriate I/O pins—there are no registers to
programmable and flexible digital decimation filter. program. Data are retrieved over a serial interface
that can support either CMOS or LVDS voltage
Figure 21 shows a block diagram of the ADS1672.
levels. In addition, the serial interface can be
The modulator is chopper-stabilized for low-drift
internally or externally clocked. This flexibility allows
performance and measures the differential input
direct connection to a wide range of digital hosts
signal V
IN
= (AINP – AINN) against the differential
including DSPs, FPGAs, and microcontrollers.
reference V
REF
= (VREFP – VREFN). The digital filter
receives the modulator signal and processes it A detection circuit monitors the conversions to
through the user-selected path. The low-latency path indicate when the inputs are out-of-range for an
provides single-cycle settling, and is ideal when using extended duration. A power-down pin (PDWN) shuts
a multiplexer or when measuring large transients. The off all circuitry when the ADS1672 is not in use.
wide-bandwidth path provides outstanding frequency
x
response with very low passband ripple, a steep
transition band, and large stop band attenuation. This
x
path is well-suited for applications that require
high-resolution measurements of high-frequency ac
x
signal content.
Figure 21. ADS1672 Block Diagram
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