Datasheet

6.1 Serial Data Interface, P2
Digital Interface www.ti.com
The P2 connector (Table 3 ) is used for the digital interface to MMB0 and ADCPro. All logic levels on P2
are 3.3V CMOS.
Table 3. P2: External Digital I/O Connector
Pin Number Signal Description
P2.1 CS Chip select, active low
Digital filter out-of-range indicator. High on
rising edge of DRDY. If conversion is in
P2.2 OTRD
range, OTRD returns low on next rising
edge of DRDY.
Serial transmit clock from processor.
P2.3 CLKX Jumper connect to P2.5 installed at
factory.
P2.4 GND System ground
P2.5 CLKR Serial receive clock from ADS1672EVM
P2.6 NC No connection
P2.7 FSX Frame sync signal from processor
P2.8 NC No connection
Frame sync return to processor (sourced
P2.9 FSR
from the DRDY output of the ADS1672)
P2.10 GND System ground
P2.11 NC No connection
P2.12 NC No connection
P2.13 DRR Serial data into processor
P2.14 NC No connection
Interrupt source to processor (sourced
P2.15 DRDY
from the DRDY output pin)
I
2
C serial shift clock (NOTE: For this
P2.16 SCL function to work, all SW1 switches should
be in the off position)
General-purpose pin. Can be used to
P2.17 GPIO
toggle start.
P2.18 GND System ground
P2.19 NC No connection
I
2
C data signal (NOTE: For this function to
P2.20 SDA work, all SW1 switches should be in the off
position)
8 ADS1672EVM and ADS1672EVM-PDK User's Guide SBAU147 – March 2009
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