Datasheet

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SBAS274H − MARCH 2003 − REVISED MAY 2007
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8
PARAMETER MEASUREMENT INFORMATION
DRDY
CLK
DOUT[15:0] Data N + 1
t
1
t
2
t
2
t
3
t
5
t
6
t
4
t
4
Data N Data N + 2
NOTE: CS and RD tied low.
Figure 1. Data Retrieval Timing (ADS1605, ADS1606 with FIFO Disabled)
RD, CS
DOUT[15:0]
t
8
t
7
Figure 2. DOUT Inactive/Active Timing (ADS1605, ADS1606 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 1 AND FIGURE 2
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
1
CLK period (1/f
CLK
)
20 25 1000 ns
1/t
1
f
CLK
1 40 50 MHz
t
2
CLK pulse width, high or low
10 ns
t
3
Rising edge of CLK to DRDY low
10 ns
t
4
DRDY pulse width high or low
4 t
1
ns
t
5
Falling edge of DRDY to data invalid
10 ns
t
6
Falling edge of DRDY to data valid
15 ns
t
7
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
15 ns
t
8
Falling edge of RD and/or CS active (low) to DOUT active.
15 ns
NOTE: DOUT[15:0] and DRDY load = 10pF.