Datasheet

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SBAS274H − MARCH 2003 − REVISED MAY 2007
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9
CLK
RESET
DRDY
DOUT[15:0]
t
10
t
9
t
12
t
3
t
11
Settled
Data
NOTE: CS and RD tied low.
Figure 3. Reset TIming (ADS1605, ADS1606 with FIFO Disabled)
TIMING REQUIREMENTS FOR FIGURE 3
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
3
Rising edge of CLK to DRDY low
10 ns
t
9
RESET pulse width
50 ns
t
10
Delay from RESET active (low) to DRDY forced high and DOUT forced low
9 ns
t
11
RESET rising edge to falling edge of CLK
−5 10 ns
t
12
Delay from DOUT active to valid DOUT (settling to 0.001%)
47
DRDY
Cycles
NOTE: DOUT[15:0] and DRDY load = 10pF.