Datasheet

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SBAS274H − MARCH 2003 − REVISED MAY 2007
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25
32/f
CLK
128/f
CLK
DRDY
RD
Figure 24. Example of Skipping Readback when FIFO Level = 4
64/f
CLK
DRDY
FIFO_LEV[2:0] 010 (Level = 4)
Change FIFO_LEV[2:0] here
100 (Level = 8)
RD
32/f
CLK
Figure 25. Example of Synchronized Change of FIFO Level from 4 to 8
ANALOG POWER DISSIPATION
An external resistor connected between the RBIAS pin
and the analog ground sets the analog current level, as
shown in Figure 26. The current is inversely proportion-
al to the resistor value. Table 6 shows the recom-
mended values of R
BIAS
for different CLK frequencies.
Notice that the analog current can be reduced when us-
ing a slower frequency CLK input because the modula-
tor has more time to settle. Avoid adding any capaci-
tance in parallel to R
BIAS
, since this will interfere with
the internal circuitry used to set the biasing.
R
BIAS
RBIAS
AGND
ADS1606
ADS1605
Figure 26. External Resistor Used to Set Analog
Power Dissipation
Table 6. Recommended R
BIAS
Resistor Values for
Different CLK Frequencies
f
CLK
DATA
RATE
R
BIAS
TYPICAL POWER
DISSIPATION WITH REFEN
HIGH
16MHz 2MHz 60kΩ 315mW
24MHz 3MHz 50kΩ 400mW
32MHz 4MHz 45kΩ 475mW
40MHz 5MHz 37kΩ 570mW
POWER DOWN (PD)
When not in use, the ADS1605/6 can be powered down
by taking the PD pin low. All circuitry will be shutdown,
including the voltage reference. To minimize the digital
current during power down, stop the clock signal sup-
plied to the CLK input. There is an internal pull-up resis-
tor of 170kΩ on the PD pin, but it is recommended that
this pin be connected to IOVDD if not used. If using the
ADS1606 with the FIFO enabled, issue a reset after ex-
iting power-down mode. Make sure to allow time for the
reference to start up after exiting power-down mode.
The internal reference typically requires 15ms. After the
reference has stabilized, allow at least 100 DRDY
cycles for the modulator and digital filter to settle before
retrieving data.