Datasheet

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SBAS274H − MARCH 2003 − REVISED MAY 2007
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24
FIFO (ADS1606 ONLY)
The ADS1606 includes an adjustable level first-in first-
out buffer (FIFO) for the output data. The FIFO allows
data to be temporarily stored within the ADS1606 to
provide more flexibility for the host controller when re-
trieving data. Pins FIFO_LEV[2:0] set the level or depth
of the FIFO. Note that these pins must be left uncon-
nected on the ADS1605. The FIFO is enabled by setting
at least one of the FIFO_LEV inputs high. Table 5
shows the corresponding FIFO level and DRDY
period
for the different combinations of FIFO_LEV[2:0] set-
tings. For the best performance when using the FIFO,
it is recommended to:
1. Set IOVDD = 3V.
2. Synchronize data retrieval with CLK.
3. Minimize loading on outputs DOUT[15:0].
4. Ensure rise and fall times on CLK and RD are 1ns
or longer.
Table 5. FIFO Buffer Level Settings for the
ADS1606
FIFO_LEV[2:0] FIFO BUFFER LEVEL DRDY PERIOD
000 0: disabled,
operates like ADS1605
8/f
CLK
001 2 16/f
CLK
010 4 32/f
CLK
011 6 48/f
CLK
100 8 64/f
CLK
101 10 80/f
CLK
110 12 96/f
CLK
111 14 112/f
CLK
FIFO Operation
The ADS1606 FIFO collects the number of output read-
ings set by the level corresponding to the
FIFO_LEV[2:0] setting. When the specified level is
reached, DRDY is pulsed high, indicating the data in the
FIFO are ready to be read. The DRDY period is a func-
tion of the FIFO level, as shown in Table 5. To read the
data, make sure CS is low (it is acceptable to tie it low)
and then take RD low. The first, or oldest, data will be
presented on the data output pins. After reading this
data, advance to the next data reading by toggling RD.
On the next falling edge of RD, the second data are
present on the data output pins. Continue this way until
all the data have been read from the FIFO, making sure
to take RD high when complete. Afterwards, wait until
DRDY toggles and repeat the readback cycle.
Figure 23 shows an example readback when
FIFO_LEV[2:0] = 010 (level = 4).
Readback considerations
The exact number of data readings set by the FIFO lev-
el must be read back each time DRDY toggles. The one
exception is that readback can be skipped entirely. In
this case, the DRDY period increases to 128 CLK peri-
od. Figure 24 shows an example when readback is
skipped with the FIFO level = 4. Do not read back more
or less readings from the FIFO than set by the level.
This interrupts the FIFO operation and can cause
DRDY to stay low indefinitely. If this occurs, the RESET
pin must be toggled followed by a RD pulse. This resets
the ADS1606 FIFO and also the digital filter, which then
must settle afterwards before valid data is ready. See
the section, Resetting the ADS1606, for more details.
Also note that the RD signal is independent of the CS
signal. Therefore, when multiple devices are used, the
RD signal should not be shared. Alternatively, individual
RD signals can be generated by performing an OR op-
eration with the CS signal.
Setting the FIFO Level
The FIFO level setting is usually a static selection that
is set when power is first applied to the ADS1606. If the
FIFO level needs to be changed after powerup, there
are two options. One is to asynchronously set the new
value on pin FIFO_LEV[2:0] then toggle RESET. Re-
member that the ADS1606 will need to settle after re-
setting. See the section, Resetting the ADS1606, for
more details. The other option avoids requiring a reset,
but needs synchronization of the FIFO level change
with the readback. The FIFO_LEV[2:0] pins have to be
changed after RD goes high after reading the first data,
but before RD goes low to read the last data from the
FIFO. The new FIFO level becomes active immediately
and the DRDY period adjusts accordingly. When de-
creasing the FIFO level this way, make sure to give ade-
quate time for readback of the data before setting the
new, smaller level. Figure 25 shows an example of a
synchronized FIFO level change from 4 to 8.
DRDY
DOUT[15:0]
(1) CS can be tied low.
(2) Data
1
is the oldest data and Data
4
is the most recent.
CS
(1)
RD
Data
1
(2)
Data
2
Data
3
Data
4
Figure 23. Example of FIFO Readback when FIFO Level = 4