Datasheet

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SBAS274H − MARCH 2003 − REVISED MAY 2007
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21
RESETTING THE ADS1605
The ADS1605 and ADS1606 (with FIFO disabled) are
asynchronously reset when the RESET
pin is taken low.
During reset, all of the digital circuits are cleared,
DOUT[15:0] are forced low, and DRDY forced high. It
is recommended that the RESET pin be released on the
falling edge of CLK. Afterwards, DRDY goes low on the
second rising edge of CLK. Allow 47 DRDY cycles for
the digital filter to settle before retrieving data. See
Figure 3 for the timing specifications.
Reset can be used to synchronize multiple ADS1605s.
All devices to be synchronized must use a common
CLK input. With the CLK inputs running, pulse RESET
on the falling edge of CLK, as shown in Figure 15. After-
wards, the converters will be converting synchronously
with the DRDY outputs updating simultaneously. After
synchronization, allow 47 DRDY cycles (t
12
) for output
data to fully settle.
RESET
ADS1605
1
CLK
DRDY
DOUT[15:0]
DRDY
1
DOUT[15:0]
1
RESET
Clock
RESET
ADS1605
2
CLK
DRDY
DOUT[15:0]
DRDY
2
DOUT[15:0]
2
CLK
RESET
DRDY
1
DOUT[15:0]
1
Synchronized
Settled
Data
Settled
Data
DRDY
2
DOUT[15:0]
2
t
12
Figure 15. Synchronizing Multiple Converters
RESETTING THE ADS1606
The ADS1606 with the FIFO enabled requires a differ-
ent reset sequence than the ADS1605, as shown in
Figure 16. Ignore any DRDY toggles that occur while
RESET is low. Release RESET on the rising edge of
CLK, then afterwards toggle RD to complete the reset
sequence.
Toggle RD to complete reset sequence
CLK
RESET
DRDY
R
D
t
26
Ignore
Figure 16. Resetting the ADS1606 with the FIFO
Enabled
After resetting, the settling time for the ADS1606 is 47
CLK cycles, regardless of the FIFO level. Therefore, for
higher FIFO levels, it takes fewer DRDY cycles to settle
because the DRDY period is longer. Table 4 shows the
number of DRDY cycles required to settle for each FIFO
level.
Table 4. ADS1606 Reset Settling
FIFO LEVEL
FILTER SETTLING TIME AFTER RESET
(t
26
in units of DRDY cycles )
2 24
4 12
6 8
8 6
10 5
12 4
14 4