Datasheet

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SBAS274H − MARCH 2003 − REVISED MAY 2007
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17
OVERVIEW
The ADS1605 and ADS1606 are high-performance delta-
sigma ADCs with a default oversampling ratio of 8. The
modulator uses an inherently stable 2-1-1 pipelined delta-
sigma modulator architecture incorporating proprietary
circuitry that allows for very linear high-speed operation.
The modulator samples the input signal at 40MSPS
(when f
CLK
= 40MHz). A low-ripple linear phase digital fil-
ter decimates the modulator output to provide data output
word rates of 5MSPS with a signal passband out to
2.45MHz. The 2X mode, enabled by a digital I/O pin,
doubles the data rate to 10MSPS by reducing the over-
sampling ratio to 4. See the 2X Mode section for more de-
tails.
Conceptually, the modulator and digital filter measure the
differential input signal, V
IN
= (AINP – AINN), against the
scaled differential reference, V
REF
= (VREFP – VREFN),
as shown in Figure 7. The voltage reference can either be
generated internally or supplied externally. An 16-bit paral-
lel data bus, designed for direct connection to DSPs, out-
puts the data. A separate power supply for the I/O allows
flexibility for interfacing to different logic families. Out-of-
range conditions are indicated with a dedicated digital out-
put pin. Analog power dissipation is controlled using an
external resistor. This allows reduced dissipation when
operating at slower speeds. When not in use, power con-
sumption can be dramatically reduced using the PD pin.
The ADS1606 incorporates an adjustable FIFO buffer for
the output data. The level of the FIFO is set by the
FIFO_LEV[2:0] pins. Other than the FIFO buffer, the
ADS1605 and ADS1606 are identical, and are referred to
together in this data sheet as the ADS1605/6.
ANALOG INPUTS (AINP, AINN)
The ADS1605/6 measures the differential signal,
V
IN
= (AINP − AINN), against the differential reference,
V
REF
= (VREFP – VREFN). The reference is scaled inter-
nally so that the full-scale differential input voltage is
1.467V
REF
. That is, the most positive measurable differ-
ential input is 1.467V
REF
, which produces the most posi-
tive digital output code of 7FFFh. Likewise, the most neg-
ative measurable differential input is –1.467V
REF
, which
produces the most negative digital output code of 8000h.
The ADS1605/6 supports a very wide range of input sig-
nals. For V
REF
= 3V, the full-scale input voltages are
±4.4V. Having such a wide input range makes out-of-
range signals unlikely. However, should an out-of-range
signal occur, the digital output OTR will go high.
To achieve the highest analog performance, it is recom-
mended that the inputs be limited to ±1.165V
REF
(−2dBFS). For V
REF
= 3V, the corresponding recom-
mended input range is ±3.78V.
The analog inputs must be driven with a differential signal
to achieve optimum performance. The recommended
common-mode voltage of the input signal,
V
CM
+
AINP ) AINN
2
, is 2.0V. For signals larger than
−2dBFS, the input common-mode voltage needs to be
raised in order to meet the absolute input voltage specifi-
cations. The Typical Characteristics show how perfor-
mance varies with input common-mode voltage.
In addition to the differential and common-mode input volt-
ages, the absolute input voltage is also important. This is
the voltage on either input (AINP or AINN) with respect to
AGND. The range for this voltage is:
* 0.1V t (AINN or AINP) t 4.6V
If either input is taken below –0.1V, ESD protection diodes
on the inputs will turn on. Exceeding 4.6V on either input
will result in degradation in the linearity performance. ESD
protection diodes will also turn on if the inputs are taken
above AVDD (+5V).
For signals below –2dBFS, the recommended absolute
input voltage is:
* 0.1V t (AINN or AINP) t 4.2V
Keeping the inputs within this range provides for optimum
performance.
Σ∆
Modulator
Digital
Filter
Parallel
Interface
Σ
1.467V
REF
1.467
V
REF
V
IN
VREFN IOVDDVREFP
Σ
AINP
AINN
OTR
2XMODE
FIFO_LEV[2:0]
DOUT[15:0]
ADS1606 Only
FIFO
Figure 7. Conceptual Block Diagram