Datasheet

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SBAS274H − MARCH 2003 − REVISED MAY 2007
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11
CLK
RESET
t
11
t
23
t
24
t
25
t
26
t
9
DRDY
R
D
Figure 6. Reset Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 6
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
9
RESET pulse width
50 ns
t
11
RESET rising edge to falling edge of CLK
−5 10 ns
t
23
RD pulse low after RESET goes high
8
CLK
Cycles
t
24
RD pulse high before first DRDY pulse after RESET goes high
8
CLK
Cycles
t
25
DRDY low after RESET goes low
8 × (FIFO level + 1)
CLK
Cycles
t
26
Delay from RESET high to valid DOUT (settling to 0.001%)
See Table 4
DRDY
Cycles