Datasheet

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SBAS274H − MARCH 2003 − REVISED MAY 2007
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10
CLK
DRDY
DOUT[15:0]
D1 D2 DL
(2)
t
2
t
2
t
16
t
17
t
21
t
15
t
20
t
18
t
19
t
1
t
13
t
14
CS
(1
)
R
D
(1) CS may be tied low.
(2) The number of data readings (DL) is set by the FIFO level.
Figure 4. Data Retrieval Timing (ADS1606 with FIFO Enabled)
RD, CS
DOUT[15:0]
t
8
t
7
Figure 5. DOUT Inactive/Active Timing (ADS1606 with FIFO Enabled)
TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
1
CLK period (1/f
CLK
)
20 25 1000 ns
t
2
CLK pulse width, high or low
10 ns
t
7
Rising edge of RD and/or CS inactive (high) to DOUT high impedance
7 15 ns
t
8
Falling edge of RD and/or CS active (low) to DOUT active.
7 15 ns
t
13
Rising edge of CLK to DRDY high
12 ns
t
14
DRDY period
8 × FIFO Level
(1)
CLK
Cycles
t
15
DRDY positive pulse width
1
CLK
Cycles
t
16
RD high hold time after DRDY goes low
0 ns
t
17
CS low before RD goes low
0 ns
t
18
RD negative pulse width
10 ns
t
19
RD positive pulse width
10 ns
t
20
RD high before DRDY toggles
2
CLK
Cycles
t
21
RD high before CS goes high
0 ns
NOTE: DOUT[15:0] and DRDY load = 10pF.
(1)
See FIFO section for more details.