Datasheet

1.2
1.0
0.8
0.6
0.4
0.2
0
-0.2
0 10 20 30 40
Time(ConversionCycles)
StepResponse
50
20
0
-20
-40
-60
-80
-100
-120
-140
0 2 4 6 108 12 14 16 18
Frequency(MHz)
Magnitude(dB)
20
f =40MHz
CLK
SYNC
ADS1602
1
CLK
FSO
DOUT
FSO
1
DOUT
1
SYNC
CLK
SYNC
ADS1602
2
CLK
FSO
DOUT
CLK
SYNC
FSO
1
FSO
2
t
STL
FSO
2
DOUT
2
ADS1602
www.ti.com SBAS341E –DECEMBER 2004– REVISED OCTOBER 2011
DATA RETRIEVAL STEP RESPONSE
Data retrieval is controlled through a simple serial Figure 47 plots the normalized step response for an
interface. The interface operates in a master fashion input applied at t = 0. The x-axis units of time are
by outputting both a frame sync indicator (FSO) and a conversion cycles. It takes 51 cycles to fully settle; for
serial clock (SCLK). Complementary outputs are f
CLK
= 40MHz, this corresponds to 20.4μs.
provided for the frame sync output (FSO), serial clock
(SCLK), and data output (DOUT). When not needed,
leave the complementary outputs unconnected.
INITIALIZING THE ADS1602
After the power supplies have stabilized, you must
initialize the ADS1602 by issuing a SYNC pulse as
shown in Figure 1. This operation needs only to be
done once after power-up and does not need to be
performed when exiting the Power-Down mode. Note
that the ADS1602 silicon was revised in June 2006.
The digital interface timing specifications were
modified slightly from the previous revision. This data
sheet reflects behavior of the latest revision. Contact
the factory for more information on the previous
revision.
Figure 47. Step Response
SYNCHRONIZING MULTIPLE ADS1602s
The SYNC input can be used to synchronize multiple
FREQUENCY RESPONSE
ADS1602s to provide simultaneous sampling. All
devices to be synchronized must use a common CLK
The linear phase FIR digital filter sets the overall
input. With the CLK inputs running, pulse SYNC on
frequency response. Figure 48 shows the frequency
the falling edge of CLK, as shown in Figure 46.
response from dc to 20MHz for f
CLK
= 40MHz. The
Afterwards, the converters will be converting
frequency response of the ADS1602 filter scales
synchronously with the FSO outputs updating
directly with CLK frequency. For example, if the CLK
simultaneously. After synchronization, FSO is held
frequency is decreased by half (to 20MHz), the
low until the digital filter has fully settled.
values on the x-axis in Figure 48 would need to be
scaled by half, with the span becoming dc to 10MHz.
Figure 49 shows the passband ripple from dc to
1200kHz (f
CLK
= 40MHz). Figure 50 shows a closer
view of the passband transition by plotting the
response from 900kHz to 1300kHz (f
CLK
= 40MHz).
Figure 48. Frequency Response
Figure 46. Synchronizing Multiple Converters
Copyright © 2004–2011, Texas Instruments Incorporated 19